MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 191

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 127: Data Output Timing –
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
All DQ values, collectively
Command
DQS or LDQS/UDQS
CK#
CK
READ
T0
Notes:
3
2
1. Commands other than NOP can be valid during this cycle.
2. DQ transitioning after DQS transitions define
3. All DQ must transition by
4.
NOP
T1
t
AC is the DQ output window relative to CK and is the long-term component of DQ skew.
CL = 3
1
t
LZ
t
AC and
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
NOP
T2
t
RPRE
t
1
t
DQSCK
t
LZ
t
DQSCK
AC
T2n
4
191
T2
t
DQSQ after DQS transitions, regardless of
NOP
T3
1
T2n
T3n
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSCK
t
T3
AC
NOP
4
T4
t
1
DQSQ window.
T3n
T4n
T4
NOP
T5
1
© 2009 Micron Technology, Inc. All rights reserved.
T4n
T5n
READ Operation
t
AC.
T5
NOP
T6
1
Don’t Care
T5n
t
t
HZ
t
HZ
RPST