MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 185

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 121: Random Read Accesses
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
Command
Address
Address
DQS
DQS
CK#
CK#
DQ
DQ
CK
CK
Notes:
READ
Bank,
READ
Bank,
Col n
Col n
T0
T0
1. D
2. BL = 2, 4, 8, or 16 (if 4, 8, or 16, the following burst interrupts the previous).
3. READs are to an active row in any bank.
4. Shown with nominal
OUT
CL = 2
n (or x, b, g) = data-out from column n (or column x, column b, column g).
READ
Bank,
READ
Bank,
Col x
Col x
T1
T1
CL = 3
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
T1n
T1n
D
t
n
OUT
AC,
READ
Bank,
READ
Bank,
Col b
Col b
T2
T2
1
185
t
DQSCK, and
D
n + 1
T2n
T2n
OUT
D
D
OUT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
n
READ
Bank,
READ
Bank,
Col g
Col g
T3
T3
OUT
x
t
DQSQ.
D
n + 1
Don’t Care
T3n
D
T3n
x + 1
OUT
OUT
D
OUT
T4
D
T4
NOP
NOP
x
OUT
b
D
x + 1
T4n
T4n
OUT
D
b + 1
OUT
© 2009 Micron Technology, Inc. All rights reserved.
Transitioning Data
READ Operation
D
T5
T5
NOP
NOP
D
OUT
b
OUT
g
T5n
T5n
D
b + 1
D
g + 1
OUT
OUT