S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 230
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S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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1
Port Integration Module (S12GPIMV1)
2.4.3.39
2.4.3.40
232
Address 0x025E (G1, G2)
Address 0x025E (G3)
Address 0x025F (G1, G2)
Address 0x025F (G3)
Read: Anytime
Write: Anytime
Read: Anytime
Field
PIEP
Reset
Reset
Reset
Reset
7-0
W
W
W
W
R
R
R
R
Port P interrupt enable—
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
PIEP7
PIFP7
Port P Interrupt Enable Register (PIEP)
0
0
0
Port P Interrupt Flag Register (PIFP)
0
0
0
7
7
7
7
PIEP6
PIFP6
0
0
0
0
0
0
6
6
6
6
Figure 2-40. Port P Interrupt Enable Register (PIEP)
Figure 2-41. Port P Interrupt Flag Register (PIFP)
Table 2-66. PIEP Register Field Descriptions
MC9S12G Family Reference Manual,
PIEP5
PIEP5
PIFP5
PIFP5
0
0
0
0
5
5
5
5
PIEP4
PIEP4
PIFP4
PIFP4
0
0
0
0
4
4
4
4
Description
PIEP3
PIEP3
PIFP3
PIFP3
3
0
3
0
3
0
3
0
Rev.1.23
PIEP2
PIEP2
PIFP2
PIFP2
0
0
0
0
2
2
2
2
Freescale Semiconductor
Access: User read/write
Access: User read/write
Access: User read/write
Access: User read/write
PIEP1
PIEP1
PIFP1
PIFP1
0
0
0
0
1
1
1
1
PIEP0
PIEP0
PIFP0
PIFP0
0
0
0
0
0
0
0
0
1
1
1
1
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