S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 591
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S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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Freescale Semiconductor
Module Base + 0x0001
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except CANE which is write once in normal and anytime in
special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1)
CLKSRC
LOOPB
LISTEN
WUPM
BORM
CANE
Field
7
6
5
4
3
2
Reset:
W
R
MSCAN Enable
0 MSCAN module is disabled
1 MSCAN module is enabled
MSCAN Clock Source — This bit defines the clock source for the MSCAN module (only for systems with a clock
generation module;
0 MSCAN clock source is the oscillator clock
1 MSCAN clock source is the bus clock
Loopback Self Test Mode — When this bit is set, the MSCAN performs an internal loopback which can be used
for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN
input is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does
normally when transmitting and treats its own transmitted message as a message received from a remote node.
In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure
proper reception of its own message. Both transmit and receive interrupts are generated.
0 Loopback self test disabled
1 Loopback self test enabled
Listen Only Mode — This bit configures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN
messages with matching ID are received, but no acknowledgement or error frames are sent out (see
Section 18.4.4.4, “Listen-Only
applications which require “hot plugging” or throughput analysis. The MSCAN is unable to transmit any
messages when listen only mode is active.
0 Normal operation
1 Listen only mode activated
Bus-Off Recovery Mode — This bit configures the bus-off state recovery mode of the MSCAN. Refer to
Section 18.5.2, “Bus-Off
0 Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol specification)
1 Bus-off recovery upon user request
Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is
applied to protect the MSCAN from spurious wake-up (see
0 MSCAN wakes up on any dominant level on the CAN bus
1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of T
CANE
0
7
= Unimplemented
CLKSRC
Figure 18-5. MSCAN Control Register 1 (CANCTL1)
Table 18-4. CANCTL1 Register Field Descriptions
6
0
Section 18.4.3.2, “Clock
MC9S12G Family Reference Manual, Rev.1.23
Recovery,” for details.
LOOPB
Mode”). In addition, the error counters are frozen. Listen only mode supports
0
5
LISTEN
System,” and
4
1
Description
Freescale’s Scalable Controller Area Network (S12MSCANV3)
Section Figure 18-43., “MSCAN Clocking
BORM
Section 18.4.5.5, “MSCAN Sleep
0
3
WUPM
2
0
Access: User read/write
SLPAK
0
1
wup
Mode”).
Scheme,”).
INITAK
0
1
593
1
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