S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 347
S9S12G64F0CLFR
Manufacturer Part Number
S9S12G64F0CLFR
Description
16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
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8.5.3
A trigger is generated if a given sequence of 2 code events is executed.
A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into
a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes.
A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry
into a range (COMPA,COMPB configured for range mode)
All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding
8.5.4
A trigger is generated immediately when one of up to 3 given events occurs
Scenario 3 is possible with S12SDBGV1 SCR encoding
8.5.5
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B
and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate
Freescale Semiconductor
SCR1=0011
SCR1=0111
SCR1=0010
State1
State1
State1
Scenario 2
Scenario 3
Scenario 4
M1
M01
M2
SCR1=0000
SCR2=0101
SCR2=0101
SCR2=0011
State1
MC9S12G Family Reference Manual, Rev.1.23
State2
State2
State2
Figure 8-29. Scenario 2b
Figure 8-28. Scenario 2a
Figure 8-30. Scenario 2c
Figure 8-31. Scenario 3
M012
M2
M2
M0
Final State
Final State
Final State
Final State
S12S Debug Module (S12SDBGV2)
349
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