S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 184

• Manufacturer Part Number: S912XEQ512J3CAGR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XEQ512J3CAGR

• Rohs: yes
• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 kB
• Data Ram Size: 32 kB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• Interface Type: CAN/SCI/SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 2 Port Integration Module (S12XEPIMV1)
Port J pin PJ[3] can be used for general purpose I/O.
Port J pin PJ[2] can be used for either general purpose I/O or as chip select output.
Port J pin PJ[1] can be used for either general purpose I/O, or with the SCI2 subsystem.
Port J pin PJ[0] can be used for either general purpose I/O, or with the SCI2 subsystem or as chip select
output.
2.4.3.12
This port is associated with the ATD0.
Port AD0 pins PAD[15:0] can be used for either general purpose I/O, or with the ATD0 subsystem.
2.4.3.13
This port is associated with the ATD1.
Port AD1 pins PAD[31:16] can be used for either general purpose I/O, or with the ATD1 subsystem.
2.4.3.14
This port is associated with the TIM module.
Port R pins PR[7:0] can be used for either general-purpose I/O, or with the channels of the standard Timer.
The TIM channels can be re-routed.
2.4.3.15
This port is associated with SCI7-4.
Port L pins PL[7:6] can be used for either general purpose I/O, or with SCI7 subsystem.
Port L pins PL[5:4] can be used for either general purpose I/O, or with SCI6 subsystem.
Port L pins PL[3:2] can be used for either general purpose I/O, or with SCI5 subsystem.
Port L pins PL[1:0] can be used for either general purpose I/O, or with SCI4 subsystem.
2.4.3.16
This port is associated with SCI3, IIC0 and chip selects.
Port L pins PL[7:6] can be used for either general purpose I/O, or with SCI3 subsystem.
Port L pins PL[5:4] can be used for either general purpose I/O, or with IIC0 subsystem.
Port L pins PL[3:0] can be used for either general purpose I/O, or with chip selects.
184
Port AD0
Port AD1
Port R
Port L
Port F
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor