S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 696

• Manufacturer Part Number: S912XEQ512J3CAGR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XEQ512J3CAGR

• Rohs: yes
• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 kB
• Data Ram Size: 32 kB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• Interface Type: CAN/SCI/SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
1. Intended for factory test purposes only.
19.3.2.1
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM
waveform is not available on the associated PWM output until its clock source begins its next cycle due to
the synchronization of PWMEx and the clock source.
696
PWMPER6
PWMPER7
PWMDTY0
PWMDTY1
PWMDTY2
PWMDTY3
PWMDTY4
PWMDTY5
PWMDTY6
PWMDTY7
PWMSDN
Register
0x001C
0x001D
0x001A
0x001B
0x001E
0x001F
0x0020
0x0021
0x0022
0x0023
0x0024
Name
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
PWM Enable Register (PWME)
The first PWM cycle after enabling the channel can be irregular.
PWMIF
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
= Unimplemented or Reserved
Figure 19-2. PWM Register Summary (Sheet 3 of 3)
PWMIE
6
6
6
6
6
6
6
6
6
6
6
MC9S12XE-Family Reference Manual Rev. 1.25
PWMRSTRT
5
0
5
5
5
5
5
5
5
5
5
5
NOTE
PWMLVL
4
4
4
4
4
4
4
4
4
4
4
3
0
3
3
3
3
3
3
3
3
3
3
PWM7IN
2
2
2
2
2
2
2
2
2
2
2
PWM7INL
Freescale Semiconductor
1
1
1
1
1
1
1
1
1
1
1
PWM7ENA
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0