S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 825

• Manufacturer Part Number: S912XEQ512J3CAGR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XEQ512J3CAGR

• Rohs: yes
• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 kB
• Data Ram Size: 32 kB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• Interface Type: CAN/SCI/SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

The period can be calculated as follows depending of APICLK:
23.3.2.6
The Reserved 06 is reserved for test purposes.
23.3.2.7
The VREGHTTR register allows to trim the VREG temperature sense.
Freescale Semiconductor
0x02F6
0x02F7
Fiption
1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details.
HTTR[3:0]
HTOEN
Reset
Reset
Field
3–0
7
W
W
R
R
Period = 2*(APIR[15:0] + 1) * 0.1 ms or period = 2*(APIR[15:0] + 1) * bus clock period
HTOEN
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled
0 The temperature sense offset is disabled
1 The temperature sense offset is enabled
Reserved 06
High Temperature Trimming Register (VREGHTTR)
High Temperature Trimming Bits — See
0
0
0
7
7
1. When trimmed within specified accuracy. See electrical specifications for details.
Table 23-9. Selectable Autonomous Periodical Interrupt Periods (continued)
APICLK
= Unimplemented or Reserved
= Unimplemented or Reserved
1
HTTR[3]
0
0
0
0
6
6
Bit
MC9S12XE-Family Reference Manual Rev. 1.25
Table 23-10. VREGHTTR field descriptions
Increases V
APIR[15:0]
0
0
0
0
5
5
FFFF
Table 23-11. Trimming Effect
Figure 23-8. Reserved 06
Figure 23-9. VREGHTTR
HT
twice of HTTR[2]
Table 23-11
0
0
0
0
4
4
Trimming Effect
Description
for trimming effects.
HTTR3
131072 * bus clock period
0
0
0
3
3
1
Selected Period
Chapter 23 Voltage Regulator (S12VREGL3V3V1)
HTTR2
0
0
0
2
2
1
HTTR1
0
0
0
1
1
1
HTTR0
0
0
0
0
0
1
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