S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 89

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S912XEQ512J3CAGR

Manufacturer Part Number
S912XEQ512J3CAGR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XEQ512J3CAGR

Rohs
yes
Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 kB
Data Ram Size
32 kB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
Interface Type
CAN/SCI/SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V

Available stocks

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Manufacturer
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Part Number:
S912XEQ512J3CAGR
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Chapter 2
Port Integration Module (S12XEPIMV1)
2.1
2.1.1
The S12XE Family Port Integration Module establishes the interface between the peripheral modules
including the non-multiplexed External Bus Interface module (S12X_EBI) and the I/O pins for all ports.
It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins.
This document covers:
Freescale Semiconductor
Revision
Number
V01.17
V01.18
V01.19
Port A and B used as address output of the S12X_EBI
Port C and D used as data I/O of the S12X_EBI
Port E associated with the S12X_EBI control signals and the IRQ, XIRQ interrupt inputs
Port K associated with address output and control signals of the S12X_EBI
Port T associated with 1 ECT module
Port S associated with 2 SCI and 1 SPI modules
Port M associated with 4 MSCAN and 1 SCI module
Port P connected to the PWM and 2 SPI modules - inputs can be used as an external interrupt source
Port H associated with 4 SCI modules - inputs can be used as an external interrupt source
Port J associated with 1 MSCAN, 1 SCI, 2 IIC modules and chip select outputs - inputs can be used
as an external interrupt source
Port AD0 and AD1 associated with two 16-channel ATD modules
Port R associated with 1 standard timer (TIM) module
Port L associated with 4 SCI modules
Introduction
Overview
Revision Date
25 Nov 2008
18 Dec 2009
02 Apr 2008
2.4.3.4/181
2.3.19/120
MC9S12XE-Family Reference Manual Rev. 1.25
Sections
Affected
Table 2-1. Revision History
• Corrected reduced drive strength to 1/5
• Separated PE1,0 bit descriptions from other PE GPIO
• Corrected alternative functions on Port K (ACC[2:0])
• Corrected functions on PE[5] (MODB) and PE[2] (WE)
• Added function independency to reduced drive and wired-or bit
• Minor corrections
descriptions
Description of Changes
89

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