MCIMX6Q4AVT10ACR Freescale Semiconductor, MCIMX6Q4AVT10ACR Datasheet - Page 114

• Manufacturer Part Number: MCIMX6Q4AVT10ACR
• Description: Processors - Application Specialized i.MX6Q
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6Q4AVT10ACR

• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 KB
• Operating Supply Voltage: 1.05 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Electrical Characteristics
4.11.12.9 Low-Power Receiver Timing
4.11.13 HSI Host Controller Timing Parameters
This section describes the timing parameters of the HSI Host Controller which are compliant with
High-Speed Synchronous Serial Interface (HSI) Physical Layer specification version 1.01.
4.11.13.1 Synchronous Data Flow
4.11.13.2 Pipelined Data Flow
114
Output
Input
First bit of
DATA
READY
FLAG
frame
Figure 79. Synchronized Data Flow READY Signal Timing (Frame and Stream Transmission)
First bit of
DATA
FLAG
READY
frame
e
SPIKE
Figure 80. Pipelined Data Flow Ready Signal Timing (Frame Transmission Mode)
A Ready can change
detected the start
Receiver has
of the Frame
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
t
N-bits Frame
NomBit
Figure 78. Input Glitch Rejection of Low-Power Receivers
t
NomBit
N-bits Frame
T
MIN-RX
Last bit of
frame
B Ready shall not
change to zero
Last bit of
2*T
frame
First bit of
frame
LPX
Receiver has captured
and stored a complete
Frame
First bit of
frame
C. Ready can change
N-bits Frame
2*T
N-bits Frame
LPX
Last bit of
maintain zero of if
receiver does not
have free space
frame
D. Ready shall
T
MIN-RX
Last bit of
frame
Last bit of
change
Ready
frame
can
E.
Freescale Semiconductor
e
F. Ready
maintain
its value
SPIKE
shall
can change
G. Ready
V
V
IH
IL