MCIMX6Q4AVT10ACR Freescale Semiconductor, MCIMX6Q4AVT10ACR Datasheet - Page 65

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MCIMX6Q4AVT10ACR

Manufacturer Part Number
MCIMX6Q4AVT10ACR
Description
Processors - Application Specialized i.MX6Q
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet

Specifications of MCIMX6Q4AVT10ACR

Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
1 GHz
Data Ram Size
256 KB
Operating Supply Voltage
1.05 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
FCBGA-624
Interface Type
I2C, I2S, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
Figure 29
Table
1
2
3
4.10
The i.MX 6Dual/6Quad GPMI controller is a flexible interface NAND Flash controller with 8-bit data
width, up to 200 MB/s I/O speed and individual chip select. It supports Asynchronous timing mode,
Source Synchronous timing mode, and Samsung Toggle timing mode separately described in the following
subsections.
Freescale Semiconductor
To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P
in the middle of DRAM_DATAxx window.
All measurements are in reference to Vref level.
Measurements were done using balanced load and 25  resistor from outputs to DRAM_VREF.
DRAM_SDCLKx_P
DRAM_SDCLKx_N
DRAM_SDQSx_P (input)
DRAM_DATAxx (input)
LP26
ID
48.
General-Purpose Media Interface (GPMI) Timing
shows the LPDDR2 read timing diagram. The timing parameters for this diagram appear in
Minimum required DRAM_DATAxx valid window width for LPDDR2
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
Parameter
Figure 29. LPDDR2 Read Cycle
Table 48. LPDDR2 Read Cycle
DATA
LP26
DATA
DATA
DATA
Symbol
DATA
DATA
Min
250
CK = 532 MHz
Electrical Characteristics
DATA
Max
DATA
Unit
ps
65

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