MCIMX6Q4AVT10ACR Freescale Semiconductor, MCIMX6Q4AVT10ACR Datasheet - Page 98
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MCIMX6Q4AVT10ACR
Manufacturer Part Number
MCIMX6Q4AVT10ACR
Description
Processors - Application Specialized i.MX6Q
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX6Q6AVT10AC.pdf
(166 pages)
Specifications of MCIMX6Q4AVT10ACR
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
1 GHz
Data Ram Size
256 KB
Operating Supply Voltage
1.05 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
FCBGA-624
Interface Type
I2C, I2S, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
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Electrical Characteristics
A frame starts with a rising edge on IPU2_CSIx_VSYNC (all the timings correspond to straight polarity
of the corresponding signals). Then IPU2_CSIx_HSYNC goes to high and hold for the entire line. Pixel
clock is valid as long as IPU2_CSIx_HSYNC is high. Data is latched at the rising edge of the valid pixel
clocks. IPU2_CSIx_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI
stops receiving data from the stream. For the next line, the IPU2_CSIx_HSYNC timing repeats. For the
next frame, the IPU2_CSIx_VSYNC timing repeats.
4.11.10.2.3 Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in
Section 4.11.10.2.2, “Gated Clock
Mode,”)
except for the IPU2_CSIx_HSYNC signal, which is not used (see
Figure
66). All incoming pixel clocks
are valid and cause data to be latched into the input FIFO. The IPU2_CSIx_PIX_CLK signal is inactive
(states low) until valid data is going to be transmitted over the bus.
Start of Frame
nth frame
n+1th frame
IPU2_CSIx_VSYNC
IPU2_CSIx_PIX_CLK
invalid
invalid
IPU2_CSIx_DATA_EN[19:0]
1st byte
1st byte
Figure 66. Non-Gated Clock Mode Timing Diagram
The timing described in
Figure 66
is that of a typical sensor. Some other sensors may have a slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered
IPU2_CSIx_VSYNC; active-high/low IPU2_CSIx_HSYNC; and rising/falling-edge triggered
IPU2_CSIx_PIX_CLK.
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
98
Freescale Semiconductor
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