MCIMX6Q4AVT10ACR Freescale Semiconductor, MCIMX6Q4AVT10ACR Datasheet - Page 116

• Manufacturer Part Number: MCIMX6Q4AVT10ACR
• Description: Processors - Application Specialized i.MX6Q
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6Q4AVT10ACR

• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 KB
• Operating Supply Voltage: 1.05 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Electrical Characteristics
4.11.13.6 Frame Transmission Mode (Synchronized Data Flow)
4.11.13.7 Frame Transmission Mode (Pipelined Data Flow)
4.11.13.8 DATA and FLAG Signal Timing Requirement for a 15 pF Load
116
t
Rise, min
t
TxToRxSkew, maxfq
t
t
EageSepRx, min
EageSepTx, min
Parameter
t
Bit, nom
READY
DATA
start bit
FLAG
READY
and t
Frame
DATA
start bit
FLAG
Frame
Figure 84. Frame Transmission Mode Transfer of Two Frames (Synchronized Data Flow)
Figure 85. Frame Transmission Mode Transfer of Two Frames (Pipelined Data Flow)
Fall, min
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
Nominal bit time
Minimum allowed rise and fall time
Maximum skew between transmitter and receiver package pins
Minimum allowed separation of signal transitions at transmitter package pins,
including all timing defects, for example, jitter and skew, inside the transmitter.
Minimum separation of signal transitions, measured at the receiver package pins,
including all timing defects, for example, jitter and skew, inside the receiver.
Description
Description
Channel
Channel
Complete N-bits Frame
bits
Complete N-bits Frame
bits
Table 75. DATA and FLAG Timing
Description
Complete N-bits Frame
Complete N-bits Frame
Freescale Semiconductor
1 Mbit/s 100 Mbit/s
1000 ns
400 ns
350 ns
50 ns
2 ns
0.5 ns
3.5 ns
10 ns
2 ns
4 ns