MCIMX6Q4AVT10ACR Freescale Semiconductor, MCIMX6Q4AVT10ACR Datasheet - Page 42
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MCIMX6Q4AVT10ACR
Manufacturer Part Number
MCIMX6Q4AVT10ACR
Description
Processors - Application Specialized i.MX6Q
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX6Q6AVT10AC.pdf
(166 pages)
Specifications of MCIMX6Q4AVT10ACR
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
1 GHz
Data Ram Size
256 KB
Operating Supply Voltage
1.05 V to 1.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
FCBGA-624
Interface Type
I2C, I2S, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
- 40 C
Number Of Timers
2
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Electrical Characteristics
4.7.2
The LPDDR2 interface mode fully complies with JESD209-2B LPDDR2 JEDEC standard release June,
2009. The DDR3/DDR3L interface mode fully complies with JESD79-3D DDR3 JEDEC standard release
April, 2008.
Table 30
1
2
3
Table 31
42
AC input logic high
AC input logic low
AC differential input high voltage
AC differential input low voltage
Input AC differential cross point voltage
Over/undershoot peak
Over/undershoot area (above OVDD
or below OVSS)
Single output slew rate, measured
between Vol(ac) and Voh(ac)
Skew between pad rise/fall asymmetry +
skew caused by SSN
AC input logic high
AC input logic low
AC differential input voltage
Input AC differential cross point voltage
Over/undershoot peak
Over/undershoot area (above OVDD
or below OVSS)
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
The typical value of Vix(ac) is expected to be about 0.5 OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
shows the AC parameters for DDR I/O operating in LPDDR2 mode.
shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode.
DDR I/O AC Parameters
Parameter
Parameter
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
2
Table 31. DDR I/O DDR3/DDR3L Mode AC Parameters
2
Table 30. DDR I/O LPDDR2 Mode AC Parameters
3
3
Vidh(ac)
Symbol
Vidl(ac)
Vih(ac)
Vix(ac)
Vil(ac)
Vpeak
Varea
t
SKD
Symbol
tsr
Vih(ac)
Vid(ac)
Vix(ac)
Vil(ac)
Vpeak
Varea
Drive impedance = 4 0 30%
Drive impedance = 60 30%
Test Condition
Relative to Vref
Test Condition
Relative to Vref
533 MHz
clk = 533 MHz
50 to Vref.
50 to Vref.
5 pF load.
5pF load.
533 MHz
—
—
—
—
—
—
—
—
—
Vref + 0.175
Vref – 0.15
0.35
Min
—
—
0
Vref + 0.22
-0.12
0.44
Min
1
1.5
—
—
—
—
0
1
1
Typ
—
—
—
—
—
—
Typ
Freescale Semiconductor
—
—
—
—
—
—
—
—
—
—
Vref – 0.175
Vref + 0.15
OVDD
Max
Vref – 0.22
0.4
0.5
—
OVDD
Max
0.44
0.12
0.35
0.3
3.5
2.5
0.1
—
V-ns
Unit
Unit
V-ns
V/ns
V
V
V
V
V
ns
V
V
V
V
V
V
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