MC68HC908GR8CD Freescale Semiconductor, MC68HC908GR8CD Datasheet - Page 110

• Manufacturer Part Number: MC68HC908GR8CD
• Description: 8-bit Microcontrollers - MCU 8 Bit 8MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908GR8CD

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: HC08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 384 B
• Operating Supply Voltage: 3 V to 5 V
• Package / Case: SOIC-28
• Mounting Style: SMD/SMT
• Data Rom Size: 64 KB
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 21
• Program Memory Type: Flash

Flash Memory
11.3 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operations.
HVEN — High-Voltage Enable Bit
MASS — Mass Erase Control Bit
ERASE — Erase Control Bit
PGM — Program Control Bit
11.4 FLASH Page Erase Operation
Use this step-by-step procedure to erase a page (64 bytes) of FLASH memory. A page consists of 64
consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The user interrupt vector
area also forms a page. Any FLASH memory page can be erased alone.
110
1. Set the ERASE bit, and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address within the page address range desired.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
7. Clear the ERASE bit.
This read/write bit enables the charge pump to drive high voltages for program and erase operations
in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for
program or erase is followed.
Setting this read/write bit configures the 8K byte FLASH array for mass erase operation.
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
1 = MASS erase operation selected
0 = MASS erase operation unselected
1 = Erase operation selected
0 = Erase operation unselected
1 = Program operation selected
0 = Program operation unselected
Address:
Reset:
Read:
Write:
$FE08
nvs
Erase
Bit 7
0
0
(min. 10μs)
Figure 11-1. FLASH Control Register (FLCR)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
(min. 1ms)
= Unimplemented
6
0
0
5
0
0
4
0
0
HVEN
3
0
MASS
2
0
ERASE
1
0
Freescale Semiconductor
PGM
Bit 0
0