MC68HC908GR8CD Freescale Semiconductor, MC68HC908GR8CD Datasheet - Page 143

• Manufacturer Part Number: MC68HC908GR8CD
• Description: 8-bit Microcontrollers - MCU 8 Bit 8MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908GR8CD

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: HC08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 384 B
• Operating Supply Voltage: 3 V to 5 V
• Package / Case: SOIC-28
• Mounting Style: SMD/SMT
• Data Rom Size: 64 KB
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 21
• Program Memory Type: Flash

Chapter 16
Input/Output Ports (I/O)
16.1 Introduction
Twenty one (21) bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable
as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with
pullup devices if configured as input port bits. The pullup devices are automatically and dynamically
disabled when a port bit is switched to output mode.
Freescale Semiconductor
Addr.
$0000
$0001
$0002
$0003
$0004
Data Direction Register A
Register Name
Port C Data Register
Port D Data Register
Port A Data Register
Port B Data Register
Connect any unused I/O pins to an appropriate logic level, either V
V
termination reduces excess current consumption and the possibility of
electrostatic damage. Not all port pins are bonded out in all packages. Care
should be taken to make any unbonded port pins an output to prevent them
from being floating inputs.
SS
. Although the I/O ports do not require termination for proper operation,
(DDRA)
(PTC)
(PTD)
(PTA)
(PTB)
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
Figure 16-1. I/O Port Register Summary
Bit 7
0
0
0
0
0
0
= Unimplemented
PTD6
6
0
0
0
0
0
NOTE
PTB5
PTD5
5
0
0
0
0
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
PTB4
PTD4
4
0
0
0
0
DDRA3
PTD3
PTA3
PTB3
3
0
0
DDRA2
PTA2
PTB2
PTD2
2
0
0
DD
or
DDRA1
PTA1
PTB1
PTC1
PTD1
1
0
DDRA0
Bit 0
PTA0
PTB0
PTC0
PTD0
0
143