MC68HC908GR8CD Freescale Semiconductor, MC68HC908GR8CD Datasheet - Page 194

• Manufacturer Part Number: MC68HC908GR8CD
• Description: 8-bit Microcontrollers - MCU 8 Bit 8MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908GR8CD

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: HC08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 384 B
• Operating Supply Voltage: 3 V to 5 V
• Package / Case: SOIC-28
• Mounting Style: SMD/SMT
• Data Rom Size: 64 KB
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 21
• Program Memory Type: Flash

System Integration Module (SIM)
19.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See
free-running after all reset states. (See
internal reset recovery sequences.)
19.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
19.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume.
interrupt entry timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). See
194
MODULE INTERRUPT
•
•
•
I BIT
R/W
IDB
IAB
INTERRUPT
MODULE
I BIT
R/W
Interrupts:
–
–
Reset
Break interrupts
IDB
IAB
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
DUMMY
DUMMY
Figure 19-9
SP
SP – 4
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
PC – 1[7:0]
Figure 19-9. Interrupt Recovery Timing
CCR
Figure 19-8
shows interrupt recovery timing.
SP – 1
SP – 3
PC – 1[15:8]
19.3.2 Active Resets from Internal Sources
A
SP – 2
SP – 2
.
Interrupt Entry Timing
X
Figure
X
SP – 3
SP – 1
19.6.2 Stop Mode
PC – 1 [7:0]
19-10.
A
SP – 4
SP
CCR
PC – 1 [15:8]
VECT H
PC
V DATA H
OPCODE
for details.) The SIM counter is
VECT L
PC + 1
V DATA L
OPERAND
Figure 19-8
START ADDR
for counter control and
Freescale Semiconductor
OPCODE
shows