MA330028 Microchip Technology, MA330028 Datasheet - Page 119

• Manufacturer Part Number: MA330028
• Description: Daughter Cards & OEM Boards dsPIC33EP64MC504 PIM
• Manufacturer: Microchip Technology

Specifications of MA330028

• Rohs: yes
• Product: Daughter Cards
• Core: dsPIC
• Description/function: Plug-in-module with dsPIC33EP64MC504 device for use with DM330021 and DM330023 motor control development board
• Interface Type: CAN, I2C, SPI
• Operating Supply Voltage: 3 to 3.6 V
• Tool Is For Evaluation Of: dsPIC33EP64MC504
• For Use With: DM330021, DM330023

REGISTER 5-1:
© 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-4
bit 3-0
Note 1:
R/SO-0
WR
U-0
—
2:
3:
4:
5:
(1)
These bits can only be reset on POR.
If this bit is set, there will be minimal power savings (I
(TVREG) before Flash memory becomes operational.
All other combinations of NVMOP<3:0> are unimplemented.
Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
Two adjacent words on a 4-word boundary are programmed during execution of this operation.
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
0 = The program or erase operation completed normally
NVMSIDL: NVM Stop-in-Idle Control bit
1 = Flash voltage regulator goes into Stand-by mode during Idle mode
0 = Flash voltage regulator is active during Idle mode
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
0011 = Memory page erase operation
0010 = Reserved
0001 = Memory double-word program operation
0000 = Reserved
R/W-0
WREN
cleared by hardware once operation is complete
automatically on any set attempt of the WR bit)
U-0
NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER
—
(1)
SO = Settable only bit
W = Writable bit
‘1’ = Bit is set
R/W-0
WRERR
U-0
—
(1)
NVMSIDL
R/W-0
U-0
Preliminary
—
(2)
(2)
(3,4)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
(5)
IDLE
(1)
), and upon exiting Idle mode there is a delay
R/W-0
U-0
NVMOP<3:0>
—
(1)
x = Bit is unknown
R/W-0
(3,4)
U-0
—
(1)
DS70657E-page 119
R/W-0
U-0
—
(1)
bit 8
bit 0