MA330028 Microchip Technology, MA330028 Datasheet - Page 43

• Manufacturer Part Number: MA330028
• Description: Daughter Cards & OEM Boards dsPIC33EP64MC504 PIM
• Manufacturer: Microchip Technology

Specifications of MA330028

• Rohs: yes
• Product: Daughter Cards
• Core: dsPIC
• Description/function: Plug-in-module with dsPIC33EP64MC504 device for use with DM330021 and DM330023 motor control development board
• Interface Type: CAN, I2C, SPI
• Operating Supply Voltage: 3 to 3.6 V
• Tool Is For Evaluation Of: dsPIC33EP64MC504
• For Use With: DM330021, DM330023

4.0
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X,
features separate program and data memory spaces
and buses. This architecture also allows the direct
access of program memory from the data space during
code execution.
FIGURE 4-1:
© 2011-2012 Microchip Technology Inc.
Note:
Note 1:
and
MEMORY ORGANIZATION
2:
This data sheet summarizes the features
of
dsPIC33EPXXXMC20X/50X,
PIC24EPXXXGP/MC20X
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section
(DS70613) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is avail-
able
(www.microchip.com).
PIC24EPXXXGP/MC20X
Memory areas are not shown to scale.
On reset, these bits are automatically copied into the device Configuration Shadow registers.
PROGRAM MEMORY MAP FOR dsPIC33EP32GP50X, dsPIC33EP32MC20X/50X,
AND PIC24EP32GP/MC20X DEVICES
from
the
4.
the
dsPIC33EPXXXGP50X,
“Program
Microchip
families
architecture
web
Memory”
and
site
Preliminary
of
Interrupt Vector Table
Flash Configuration
(11K instructions)
GOTO Instruction
Unimplemented
Reset Address
Flash Memory
User Program
(Read ‘0’s)
Reserved
Reserved
Reserved
Reserved
USERID
Latches
DEVID
Bytes
Write
(1)
4.1
The
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X,
and
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit PC during program
execution, or from table operation or data space
remapping as described in
Program and Data Memory
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD operations, which use TBLPAG<7> to read
Device ID sections of the configuration memory space.
The program memory maps, which are presented by
device family and memory size, are shown in
Figure 4-1
program
PIC24EPXXXGP/MC20X
Program Address Space
0x800FF6
0x800FF8
0x000000
0x000002
0x000004
0x0001FE
0x000200
0x0057EA
0x0057EC
0x0057FE
0x005800
0x7FFFFE
0x800000
0x800FFE
0x801000
0xF9FFFE
0xFA0000
0xFA0002
0xFA0004
0xFEFFFE
0xFF0000
0xFF0002
0xFF0004
0xFFFFFE
through
address
Figure
4-5.
memory
Section 4.8 “Interfacing
Spaces”.
devices
DS70657E-page 43
space
is
of
the
4M