MA330028 Microchip Technology, MA330028 Datasheet - Page 270

• Manufacturer Part Number: MA330028
• Description: Daughter Cards & OEM Boards dsPIC33EP64MC504 PIM
• Manufacturer: Microchip Technology

Specifications of MA330028

• Rohs: yes
• Product: Daughter Cards
• Core: dsPIC
• Description/function: Plug-in-module with dsPIC33EP64MC504 device for use with DM330021 and DM330023 motor control development board
• Interface Type: CAN, I2C, SPI
• Operating Supply Voltage: 3 to 3.6 V
• Tool Is For Evaluation Of: dsPIC33EP64MC504
• For Use With: DM330021, DM330023

REGISTER 18-2:
DS70657E-page 270
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4-2
bit 1-0
Note 1:
SSEN
R/W-0
U-0
—
2:
3:
(2)
The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
This bit must be cleared when FRMEN = 1.
Do not set both Primary and Secondary prescalers to the value of 1:1.
Unimplemented: Read as ‘0’
DISSCK: Disable SCKx Pin bit (SPI Master modes only)
1 = Internal SPI clock is disabled, pin functions as I/O
0 = Internal SPI clock is enabled
DISSDO: Disable SDOx Pin bit
1 = SDOx pin is not used by the module; pin functions as I/O
0 = SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data is sampled at end of data output time
0 = Input data is sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
CKE: SPIx Clock Edge Select bit
1 = Serial output data changes on transition from active clock state to idle clock state (refer to bit 6)
0 = Serial output data changes on transition from idle clock state to active clock state (refer to bit 6)
SSEN: Slave Select Enable bit (Slave mode)
1 = SSx pin is used for Slave mode
0 = SSx pin is not used by module. Pin is controlled by port function
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
SPRE<2:0>: Secondary Prescale bits (Master mode)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
•
•
•
000 = Secondary prescale 8:1
PPRE<1:0>: Primary Prescale bits (Master mode)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
R/W-0
CKP
U-0
—
SPI
X
CON1: SPI
W = Writable bit
‘1’ = Bit is set
MSTEN
R/W-0
U-0
—
X
CONTROL REGISTER 1
DISSCK
R/W-0
R/W-0
(1)
Preliminary
SPRE<2:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
DISSDO
R/W-0
R/W-0
(3)
(3)
(3)
MODE16
R/W-0
R/W-0
© 2011-2012 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
SMP
PPRE<1:0>
CKE
R/W-0
R/W-0
(3)
(1)
bit 8
bit 0