MA330028 Microchip Technology, MA330028 Datasheet - Page 203

• Manufacturer Part Number: MA330028
• Description: Daughter Cards & OEM Boards dsPIC33EP64MC504 PIM
• Manufacturer: Microchip Technology

Specifications of MA330028

• Rohs: yes
• Product: Daughter Cards
• Core: dsPIC
• Description/function: Plug-in-module with dsPIC33EP64MC504 device for use with DM330021 and DM330023 motor control development board
• Interface Type: CAN, I2C, SPI
• Operating Supply Voltage: 3 to 3.6 V
• Tool Is For Evaluation Of: dsPIC33EP64MC504
• For Use With: DM330021, DM330023

12.0
The Timer1 module is a 16-bit timer that can operate as
a free-running interval timer/counter.
The Timer1 module has the following unique features
over other timers:
• Can be operated in Asynchronous Counter mode
• The external clock input (T1CK) can optionally be
A block diagram of Timer1 is shown in
FIGURE 12-1:
© 2011-2012 Microchip Technology Inc.
from an external clock source
synchronized to the internal device clock and the
clock synchronization is performed after the
prescaler
Note 1: This data sheet summarizes the features
T1CK
Note 1: F
2: Some registers and associated bits
TIMER1
of
dsPIC33EPXXXMC20X/50X,
PIC24EPXXXGP/MC20X
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 11. “Timers”
(DS70362) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
P
the
is the peripheral clock.
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TCKPS<1:0>
F
Prescaler
P
(1)
(/n)
dsPIC33EPXXXGP50X,
TCKPS<1:0>
Prescaler
Sync
Gate
(/n)
Figure
families
Sync
12-1.
TSYNC
and
Preliminary
Falling Edge
of
in
Detect
0
1
TGATE
TCS
The Timer1 module can operate in one of the following
modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (F
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
The Timer modes are determined by the following bits:
• Timer Clock Source Control bit (TCS): T1CON<1>
• Timer Synchronization Control bit (TSYNC):
• Timer Gate Control bit (TGATE): T1CON<6>
Timer control bit setting for different operating modes
are given in the
TABLE 12-1:
10
00
x1
Timer
Gated timer
Synchronous
counter
Asynchronous
counter
T1CON<2>
Mode
Comparator
TMR1
PR1
T1CLK
Table
TIMER MODE SETTINGS
Equal
Reset
TCS
12-1.
0
0
1
1
1
0
TGATE
TGATE
Set T1IF flag
Latch
0
1
x
x
DS70657E-page 203
CLK
Data
Edge-control
TSYNC
CTMU
Logic
x
x
1
0
CY
).