MA330028 Microchip Technology, MA330028 Datasheet - Page 156

• Manufacturer Part Number: MA330028
• Description: Daughter Cards & OEM Boards dsPIC33EP64MC504 PIM
• Manufacturer: Microchip Technology

Specifications of MA330028

• Rohs: yes
• Product: Daughter Cards
• Core: dsPIC
• Description/function: Plug-in-module with dsPIC33EP64MC504 device for use with DM330021 and DM330023 motor control development board
• Interface Type: CAN, I2C, SPI
• Operating Supply Voltage: 3 to 3.6 V
• Tool Is For Evaluation Of: dsPIC33EP64MC504
• For Use With: DM330021, DM330023

REGISTER 9-2:
DS70657E-page 156
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11
bit 10-8
bit 7-6
bit 5
Note 1:
R/W-0
R/W-0
ROI
2:
3:
4:
PLLPOST<1:0>
This bit is cleared when the ROI bit is set and an interrupt occurs.
This register resets only on a Power-on Reset (POR).
DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock and peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
DOZE<2:0>: Processor Clock Reduction Select bits
111 = F
110 = F
101 = F
100 = F
011 = F
010 = F
001 = F
000 = F
DOZEN: Doze Mode Enable bit
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock and peripheral clock ratio forced to 1:1
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default)
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11 = Output divided by 8
10 = Reserved
01 = Output divided by 4 (default)
00 = Output divided by 2
Unimplemented: Read as ‘0’
R/W-0
R/W-1
CLKDIV: CLOCK DIVISOR REGISTER
CY
CY
CY
CY
CY
CY
CY
CY
divided by 128
divided by 64
divided by 32
divided by 16
divided by 8 (default)
divided by 4
divided by 2
divided by 1
DOZE<2:0>
y = Value set from Configuration bits on POR
W = Writable bit
‘1’ = Bit is set
R/W-1
U-0
—
(3)
(1,4)
R/W-1
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DOZEN
R/W-0
R/W-0
(2)
(1,4)
(3)
PLLPRE<4:0>
R/W-0
R/W-0
© 2011-2012 Microchip Technology Inc.
FRCDIV<2:0>
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0