NAND01GW3B2CN6E NUMONYX, NAND01GW3B2CN6E Datasheet - Page 15
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NAND01GW3B2CN6E
Manufacturer Part Number
NAND01GW3B2CN6E
Description
IC FLASH 1GBIT 48TSOP
Manufacturer
NUMONYX
Specifications of NAND01GW3B2CN6E
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
1G (128M x 8)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP
Cell Type
NAND
Density
1Gb
Access Time (max)
25us
Interface Type
Parallel
Boot Type
Not Required
Address Bus
8b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
128M
Supply Current
30mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NAND01GW3B2CN6E
Manufacturer:
Numonyx
Quantity:
5
Part Number:
NAND01GW3B2CN6E
Manufacturer:
ST
Quantity:
20 000
NAND01G-B2C
3
3.1
3.2
3.3
3.4
3.5
3.6
Signal descriptions
See
connected to this device.
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used to input the selected address, output the data during a read
operation or input a command or data during a write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
Inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 devices. They are used to output the data
during a read operation or input data during a write operation. Command and address
inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, V
High, V
standby mode.
Read Enable (R)
The Read Enable pin, R, controls the sequential data output during read operations. Data is
valid t
column address counter by one.
Figure 2: Logic
RLQV
IH
, while the device is busy, the device remains selected and does not go into
after the falling edge of R. The falling edge of R also increments the internal
diagram, and
Table 3: Signal
IL
, the device is selected. If Chip Enable goes
names, for a brief overview of the signals
Signal descriptions
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