NAND01GW3B2CN6E NUMONYX, NAND01GW3B2CN6E Datasheet - Page 25

• Manufacturer Part Number: NAND01GW3B2CN6E
• Description: IC FLASH 1GBIT 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND01GW3B2CN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 1G (128M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Cell Type: NAND
• Density: 1Gb
• Access Time (max): 25us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 128M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

NAND01G-B2C
6.2
Cache read
The cache read operation is used to improve the read throughput by reading data using the
cache register. Since the device has only one cache register, serial data output on one page
may be executed while data from another page is read into the cache register.
A Page Read command must be issued prior to the Sequential or Random Cache Read
command in a cache read sequence. The Cache Read command can be issued only after
the read function is complete (SR6 = ‘1’).
A cache read operation consists of three steps (see
1.
2.
3.
The start address must be at the beginning of a page (column address = 00h, see
and
see
The Ready/Busy signal can be used to monitor the start of the operation. During the latency
period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if
the device is internally downloading page n+1.
Once the cache read operation has started, the status register can be read using the Read
Status Register command.
During the operation, SR5 can be read, to find out whether the internal reading is ongoing
(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the cache register is
ready to download new data.
To exit the cache read operation an Exit Cache Read command must be issued (see
Table
After the device has internally read page n, the user is allowed to download data of that
page by toggling R, but the device will not trigger internally the reading of a next page.
Figure
Table
One bus cycle is required to setup the Cache Read command (the same as the
standard Read command)
Four (refer to
address. If the host does not enter an address, the next sequential page is read.
One bus cycle is required to issue the Cache Read Confirm command to start the
P/E/R controller.
10).
9). This allows the data to be output uninterrupted after the latency time (t
10.
Table 6
and
Table
7) bus cycles are then required to input the start
Table 10:
Commands):
Device operations
Table 8
BLBH1
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