NAND01GW3B2CN6E NUMONYX, NAND01GW3B2CN6E Datasheet - Page 18
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NAND01GW3B2CN6E
Manufacturer Part Number
NAND01GW3B2CN6E
Description
IC FLASH 1GBIT 48TSOP
Manufacturer
NUMONYX
Specifications of NAND01GW3B2CN6E
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
1G (128M x 8)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP
Cell Type
NAND
Density
1Gb
Access Time (max)
25us
Interface Type
Parallel
Boot Type
Not Required
Address Bus
8b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
128M
Supply Current
30mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NAND01GW3B2CN6E
Manufacturer:
Numonyx
Quantity:
5
Part Number:
NAND01GW3B2CN6E
Manufacturer:
ST
Quantity:
20 000
Bus operations
4.5
4.6
18/67
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low. The data is output sequentially using the Read Enable
signal.
See
Write Protect
Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
Standby
When Chip Enable is High the memory enters standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
1. Only for x16 devices.
2. WP must be V
Table 6.
1. Any additional address input cycles will be ignored.
Bus cycle
Command input
Bus operation
Address input
Write Protect
Data output
Data input
Figure 24
Standby
2
3
1
4
nd
st
rd
th
(1)
Bus operations
Address insertion, x8 devices
and
IH
I/O7
A19
A27
V
A7
when issuing a program or erase command.
IL
Table 25
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
I/O6
A18
A26
V
AL
V
V
V
V
A6
X
X
IH
IL
IL
IL
IL
for details of the timings requirements.
V
CL
V
V
V
X
X
IH
IL
IL
IL
I/O5
A17
A25
V
A5
IL
Falling
V
V
V
R
X
X
IH
IH
IH
I/O4
A16
A24
V
A4
Rising
Rising
Rising
IL
V
W
X
X
IH
V
I/O3
A11
A15
A23
A3
WP
X
IL
V
V
X
X
D
(2)
IH
/V
IL
D
Data output
I/O0 - I/O7
Command
Data input
I/O2
Address
A10
A14
A22
A2
X
X
I/O1
A13
A21
NAND01G-B2C
A1
A9
I/O8 - I/O15
Data output
Data input
X
X
X
X
I/O0
A12
A20
A0
A8
(1)