MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 14

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Mode Register (MR)
Burst Length
Burst Type
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
The mode register is used to define the specific mode of operation of the DDR2 SDRAM
device. This definition includes the selection of a burst length (BL), burst type, CAS
latency (CL), operating mode, DLL reset, write recovery, and power-down mode as
shown in Figure 5, Mode Register (MR) Definition. Contents of the mode register can be
altered by re-executing the LOAD MODE (LM) command. If the user chooses to modify
only a subset of the MR variables, all variables (M0–M14) must be programmed when
the LOAD MODE command is issued.
The mode register is programmed via the LM command (bits BA0–BA1/BA2 all = 0) and
other bits (M0–M13 or will retain the stored information until it is programmed again or
the device loses power (except for bit M8, which is self-clearing). Reprogramming the
mode register will not alter the contents of the memory array, provided it is performed
correctly.
The LOAD MODE command can only be issued (or reissued) when all banks are in the
precharged state. The controller must wait the specified time
subsequent operations such as an ACTIVE command. Violating either of these require-
ments will result in unspecified operation.
Burst length is defined by bits M0–M2 as shown in Figure 5 on page 15. Read and write
accesses to the DDR2 SDRAM device are burst-oriented, with BL being programmable to
either four or eight. The BL determines the maximum number of column locations that
can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to BL is effectively
selected. All accesses for that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached. The block is uniquely selected by A2–
Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most significant column
address bit for a given configuration). The remaining (least significant) address bit(s) is
(are) used to select the starting location within the block. The programmed BL applies to
both READ and WRITE bursts.
Accesses within a given burst may be programmed to be either sequential or interleaved.
The burst type is selected via bit M3 as shown in Figure 5 on page 15. The ordering of
accesses within a burst is determined by BL, the burst type, and the starting column
address as shown in Table 6 on page 16. DDR2 SDRAM devices support 4-bit burst and
8-bit burst modes only. For 8-bit burst mode, full interleave address ordering is sup-
ported; however, sequential address ordering is nibble-based.
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
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©2004, 2005 Micron Technology, Inc. All rights reserved.
t
MRD before initiating any
Mode Register (MR)