MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 39

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLL and Register Specifications
Table 19:
Table 20:
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
Register
Symbol
(bit pattern
by JESD82)
I
V
V
I
DDD
DD
C
OH
I
OL
SSTL
I
I
Dynamic operating – per each
Dynamic operating – per each
Dynamic operating – clock
Register Timing Requirements and Switching Characteristics
Register Electrical Characteristics
Note: 1
Symbol
data input, 1:1 mode
data input, 1:2 mode
f
t
clock
t
inact
Static operating
t
t
t
act
su
w
Static standby
h
Parameter
Data inputs
CK and CK#
All inputs
Notes: 1. Timing and switching specifications for the register listed above are critical for proper
RESET
only
Differential inputs
Differential inputs
Clock frequency
Pulse duration
2. This parameter is not necessarily production tested.
3. Data inputs must be LOW a minimum time of t
4. Data and clock inputs must be held at valid levels (not floating) a minimum time of t
inactive time
Parameter
active time
Setup time
Hold time
operation of the DDR2 SDRAM Registered DIMMs. These are meant to be a subset of the
parameters for the specific device used on the module. Detailed information for this regis-
ter is available in JEDEC Standard JESD82.
(MAX), after RESET# is taken LOW.
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
RESET# = V
RESET# = V
RESET# = V
CK# switching 50% duty cycle; One data input
CK# switching 50% duty cycle; One data input
RESET# = V
Data before CK HIGH, CK# LOW
Data before CK HIGH, CK# LOW
ODT, CKE, and data before CK
and CK# switching 50% duty cycle
switching at
switching at
OKE, CKE, and data after CK
DD
DD
V
DD
, V
, V
ICR
DD
HIGH, CK# LOW
HIGH, CK# LOW
, V
I
I
V
V
V
= V
= V
= 0.9V, V
, V
Condition
I
RESET# = GND
I
I
I
39
= V
I
= V
= V
= V
Condition
OH
I
I
IH
IH
OL
t
t
= V
CK/2, 50% duty cycle
CK/2, 50% duty cycle
(
(
REF
IH
AC
AC
DD
DD
= -6 mA
= 6 mA
(
IH
) or V
AC
) or V
±250mV
or GND
or GND
(
ID
AC
) or V
= 600mV
Micron Technology, Inc., reserves the right to change products or specifications without notice.
) or V
IL
IL
(
(
AC
AC
IL
(
), I
), I
IL
AC
(
AC
0
0
), I
PLL and Register Specifications
= 0; CK and
= 0; CK and
act
), I
0
(MAX), after RESET# is taken HIGH.
= 0; CK
V
0°C ≤ T
0
DD
= 0
Min
0.50
0.7
0.5
0.5
–
1
–
–
= +1.8V ±0.1V
OPR
©2004, 2005 Micron Technology, Inc. All rights reserved.
Varies by
Varies by
Varies by
V
0°C ≤ T
Varies
DD
≤ +55°C
Min
mfr
mfr
mfr
1.2
2.5
Max
–
–
–
–
2
270
10
15
= +1.8V ±0.1V
–
–
–
–
–
OPR
Varies by
Varies by
Varies by
≤ +55°C
Varies
Max
Units
100
mfr
mfr
mfr
MHz
.05
3.5
40
–
5
3
ns
ns
ns
ns
ns
ns
Notes
Units
2, 3
2, 4
mA
µA
µA
µA
pF
inact
V
V