MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 38

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
29.
30.
31. No more than 4 bank ACTIVE commands may be issued in a given
32.
33. Value is minimum pulse width, not the number of clock registrations.
34. Applicable to READ cycles only. WRITE cycles generally require additional time due
35.
36. This parameter is not referenced to a specific voltage level, but specified when the
37. When DQS is used single-ended, the minimum limit is reduced by 100ps.
t
prior to CK, CK# being removed in a system RESET condition.
t
t
DDR2 devices, regardless of the number of banks already open or closed.
t
the number of banks already open or closed. If a single-bank PRECHARGE command
is issued,
to WRITE recovery time (
t
clock edges. CKE must remain at the valid input level the entire time it takes to
achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not tran-
sition from its valid level during the time period of
device output is no longer driving (
DELAY is calculated from
ISXR is equal to
RRD(MIN) restriction still applies. The
RPA timing applies when the PRECHARGE(ALL) command is issued, regardless of
CKE (MIN) of 3 clocks means CKE must be registered on three consecutive positive
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
t
RP timing applies.
t
IS and is used for CKE setup time during self refresh exit.
t
WR) during auto precharge.
t
38
IS +
t
RPA (MIN) applies to all 8-bank DDR2 devices.
t
CK +
t
RPST) or beginning to drive (
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
IH so that CKE registration LOW is guaranteed
t
FAW(MIN) parameter applies to all 8-bank
t
IS + 2 ×
©2004, 2005 Micron Technology, Inc. All rights reserved.
t
CK +
t
t
RPRE).
IH.
t
FAW(MIN) period.
Notes