MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 37

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
12. This is not a device limit. The device will operate with a negative value, but system
13. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com-
14. The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs. How-
15. Each byte lane has a corresponding DQS.
16. CK and CK# input slew rate must be ≥ 1V/ns (≥ 2 V/ns if measured differentially).
17. The data valid window is derived by achieving other specifications -
18. The period jitter (
19. MIN(
20.
21. READs and WRITEs with auto precharge are allowed to be issued before
22. V
23.
24. The minimum READ to internal PRECHARGE time. This parameter is only applicable
25. Operating frequency is only allowed to change during self refresh mode, precharge
26. ODT turn-on time
27. ODT turn-off time
28. This parameter has a two clock minimum requirement at any
performance could be degraded due to bus turnaround.
mand. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on
ever, a REFRESH command must be asserted at least once every 70.3µs or
(MAX). To ensure all rows of all banks are properly refreshed, 8,192 REFRESH com-
mands must be issued every 64ms.
t
tion to the clock duty cycle and a practical data valid window can be derived.
age or nominal clock allowed in either the positive or negative direction. JEDEC spec-
ifies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter
values should be 20 percent less than noted in the table (DLL locked). Refer to the
256Mb, 512Mb, or 1Gb DDR2 SDRAM discrete data sheet for full jitter specifications.
high time as provided to the device (i.e., this value can be greater than the minimum
specification limits for
period, less the half period jitter [
jitter due to cross talk [
t
device CK and CK# inputs.
satisfied since
SDRAM data sheet for more detail.
t
round to the next highest integer.
refers to the
3.75ns with
clocks = 8 clocks.
when
withstanding,
automatically delay the internal PRECHARGE command until
satisfied.
power-down mode, and system reset condition.
begins to turn on. ODT turn-on time
on. Both are measured from
ODT turn off time
t
DQSQ, and
HP (MIN) is the lesser of
DAL = (nWR) + (
AOFD.
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
IL
/V
t
IH
CL,
t
RTP/(2 ×
DDR2 overshoot/undershoot. Refer to the 256Mb, 512Mb, or 1Gb DDR2
t
CH) refers to the smaller of the actual clock low time and the actual clock
t
t
t
WR programmed to four clocks.
QH (
WR parameter stored in the MR[11,10,9]. Example: For -53E at
t
t
RAS (MIN) has to be satisfied as well. The DDR2 SDRAM device will
RAS lockout feature is supported in DDR2 SDRAM devices.
t
CK) > 1. If
t
RP/
t
t
JIT
QH =
t
t
t
AOF (MAX) is when the bus is in High-Z. Both are measured from
AON (MIN) is when the device leaves High-Z and ODT resistance
AOF (MIN) is when the device starts to turn off ODT resistance.
per
t
CK): For each of the terms above, if not already an integer,
t
t
CL and
JIT(cross talk)] into the clock traces.
) is the maximum deviation in the clock period from the aver-
t
HP -
t
CL minimum and
37
t
RTP/(2 ×
t
AOND.
t
QHS). The data valid window derates in direct propor-
t
CH). For example,
t
JIT(HP)] of the clock source, and less the half period
t
CK refers to the application clock period; nWR
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
CK) ≤ 1, then equation AL + BL/2 applies. Not-
AON (MAX) is when the ODT resistance is fully
t
t
CH minimum actually applied to the
DAL = 4 + (15 ns/3.75 ns) clocks = 4 +(4)
t
CL and
t
DQSS.
©2004, 2005 Micron Technology, Inc. All rights reserved.
t
CH are = 50 percent of the
t
t
CK.
RAS (MIN) has been
t
HP (
t
RAS (MIN) is
t
CK/2),
t
RFC
t
CK =
Notes