MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 19

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Extended Mode Register (EMR)
DLL Enable/Disable
Output Drive Strength
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, output drive strength, ODT
(R
DQS# enable/disable, RDQS/RDQS# enable/disable, and OUTPUT disable/enable.
These functions are controlled via the bits shown in Figure 7 on page 20. The extended
mode register is programmed via the LOAD MODE (LM) command and will retain the
stored information until it is programmed again or the device loses power. Reprogram-
ming the extended mode register will not alter the contents of the memory array, pro-
vided it is performed correctly.
The extended mode register must be loaded when all banks are idle and no bursts are in
progress, and the controller must wait the specified time
subsequent operation. Violating either of these requirements could result in unspecified
operation.
The DLL may be enabled or disabled by programming bit E0 during the LOAD MODE
command as shown in Figure 7 on page 20. The DLL must be enabled for normal opera-
tion. DLL enable is required during power-up initialization and upon returning to nor-
mal operation after having disabled the DLL for the purpose of debugging or evaluation.
Enabling the DLL should always be followed by resetting the DLL using a LOAD MODE
command.
The DLL is automatically disabled when entering self refresh operation and is automati-
cally re-enabled and reset upon exit of self refresh operation.
Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur
before a READ command can be issued to allow time for the internal clock to be syn-
chronized with the external clock. Failing to wait for synchronization to occur may result
in a violation of the
The output drive strength is defined by bit E1 as shown in Figure 7, Extended Mode Reg-
ister Definition. The normal drive strength for all outputs are specified to be SSTL_18.
Programming bit E1 = 0 selects normal (100 percent) drive strength for all outputs.
Selecting a reduced drive strength option (bit E1 = 1) will reduce all outputs to approxi-
mately 60 percent of the SSTL_18 drive strength. This option is intended for the support
of the lighter load and/or point-to-point environments.
TT
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
), posted CAS additive latency (AL), off-chip driver impedance calibration (OCD),
t
AC or
t
DQSCK parameters.
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Extended Mode Register (EMR)
t
MRD before initiating any
©2004, 2005 Micron Technology, Inc. All rights reserved.