MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 16

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Operating Mode
DLL Reset
Write Recovery
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
Table 6:
Burst Definition
The normal operating mode is selected by issuing a LOAD MODE command with bit M7
set to zero, and all other bits set to the desired values as shown in Figure 5 on page 15.
When bit M7 is ‘1,’ no other bits of the mode register are programmed. Programming bit
M7 to ‘1’ places the DDR2 SDRAM device into a test mode that is only used by the Man-
ufacturer and should NOT be used. No operation or functionality is guaranteed if M7 bit
is ‘1.’
DLL reset is defined by bit M8 as shown in Figure 5. Programming bit M8 to ‘1’ will acti-
vate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value
of ‘0’ after the DLL RESET function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ
command can be issued to allow time for the internal clock to be synchronized with the
external clock. Failing to wait for synchronization to occur may result in a violation of
the
Write recovery (WR) time is defined by bits M9–M11 as shown in Figure 5. The WR Regis-
ter is used by the DDR2 SDRAM device during WRITE with AUTO PRECHARGE opera-
tion. During WRITE with AUTO PRECHARGE operation, the DDR2 SDRAM device
delays the internal AUTO PRECHARGE operation by WR clocks (programmed in bits
M9–M11) from the last data burst.
Write Recovery (WR) values of 2, 3, 4, 5, or 6 clocks may be used for programming bits
M9–M11. The user is required to program the value of write recovery, which is calcu-
lated by dividing
next integer; WR [cycles] =
unknown operation or incompatibility with future versions may result.
BursT Length
t
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
AC or
4
8
t
DQSCK parameters.
Starting Column
t
WR (in ns) by
(A2, A1, A0)
Address
0 0 0
0 0 1
0 1 0
0 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
t
WR [ns] /
16
t
CK (in ns) and rounding up a noninteger value to the
Burst Type = Sequential
t
CK [ns]. Reserved states should not be used as
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0,1,2,3,4,5,6,7
1,2,3,0,5,6,7,4
2,3,0,1,6,7,4,5
3,0,1,2,7,4,5,6
4,5,6,7,0,1,2,3
5,6,7,4,1,2,3,0
6,7,4,5,2,3,0,1
7,4,5,6,3,0,1,2
Order of Accesses Within a Burst
0,1,2,3
1,2,3,0
2,3,0,1
3,0,1,2
©2004, 2005 Micron Technology, Inc. All rights reserved.
Mode Register (MR)
burst type = Interleaved
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
0,1,2,3
1,0,3,2
2,3,0,1
3,2,1,0