MT9HVF3272KY-667B1 Micron Technology Inc, MT9HVF3272KY-667B1 Datasheet - Page 28

• Manufacturer Part Number: MT9HVF3272KY-667B1
• Description: MODULE DDR2 256MB 244MDIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9HVF3272KY-667B1

• Memory Type: DDR2 SDRAM
• Memory Size: 256MB
• Speed: 667MT/s
• Package / Case: 244-MDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 32Mx72
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.71A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
Table 13:
Table 14:
Capacitance
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C32_64_128x72K_2.fm - Rev. B 11/05 EN
Speed Grade
-40E
-53E
-667
Speed Grade
-40E
-53E
-667
DD
7 Conditions
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All bank interleave READ operation
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All bank interleave READ operation
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DD
A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
7 Timing Patterns – 256MB and 512MB
7 Timing Patterns – 1GB
Table 13, and Table 14, specify detailed timing requirements for I
required if timing parameter changes are made to the specification.
Legend: A = active; RA = read auto precharge; D = deselect. All banks are being inter-
leaved at minimum
address bus inputs are STABLE during DESELECTs. I
At DDR2 data rates, Micron encourages designers to simulate the performance of the
module to achieve optimum values. When inductance and delay parameters associated
with trace lengths are used in simulations, they are significantly more accurate and real-
istic than a gross estimation of module capacitance. Simulations can then render a con-
siderably more accurate result. JEDEC modules are now designed by using simulations
to close timing budgets.
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 VLP Reg. MiniDIMM
t
RC (I
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) without violating
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28
7 Timing Patterns
7 Timing Patterns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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RRD (I
Specifications and Conditions
OUT
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= 0mA.
) using a BL = 4. Control and
©2004, 2005 Micron Technology, Inc. All rights reserved.
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7. Changes will be