EASY 6996M CPU Infineon Technologies, EASY 6996M CPU Datasheet
EASY 6996M CPU
Specifications of EASY 6996M CPU
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EASY 6996M CPU Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Egress Tag Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Samurai-6M/6MX (ADM6996M/MX) Block Diagram ...
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List of Tables Table 1 Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 50 Pin Description(QFP128 ...
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Product Overview 1.1 Samurai-6M/6MX (ADM6996M/MX) Overview The Samurai-6M/6MX (ADM6996M/MX high performance, low cost, highly integrated (Controller, PHY and Memory) four 10M/100M auto-detect Half/Full duplex switch ports with TX/FX interfaces and two MII port with one MII supporting ...
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VLAN VLAN groups are implemented by full 12 bits VID matching • MAC clone function to enable multiple WAN application • TP interface Auto MDIX function for auto TX/RX swap by strapping-pin. • Interrupt pin, ...
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Block Diagram 10/100M MAC Twisted Pair Interface RXP7 A/D CONVERTER RXN7 TXP7 DRIVER TXN7 BIAS Figure 1 Samurai-6M/6MX (ADM6996M/MX) Block Diagram 1.5 Data Lengths qword: 64 bits dword: 32 bits word: 16 bits byte: 8 bits nibble: 4 bits ...
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Interface Description This chapter describes the interface descriptions for the Samurai-6M/6MX (ADM6996M/MX) • Pin Diagram • Abbreviations • Pin Description by Function 2.1 Pin Diagram Figure 2 shows the pin diagram for the Samurai-6M/6MX (ADM6996M/MX). 103 P4TXD3 104 P4TXD2 ...
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Abbreviations Standard abbreviations for I/O tables: Table 1 Abbreviations for Pin Type Abbreviations Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. AO Output. Analog levels. ...
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Note: Table 1 can be used for reference. Table 3 IO Signals Ball No. Name Network Media Connection 33 RXP_4 29 RXP_3 21 RXP_2 14 RXP_1 6 RXP_0 32 RXN_4 30 RXN_3 22 RXN_2 15 RXN_1 7 RXN_0 37 TXP_4 ...
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Table 3 IO Signals (cont’d) Ball No. Name 101 MMII_P4RXD2 PMII_P4RXD2 100 MMII_P4RXD1 PMII_P4RXD1 73 MMII_P4RXDV PMII_P4RXDV 39 MII_P4RXER 77 MMII_P4CRS PMII_P4CRS 78 MMII_P4COL PMII_P4COL Data Sheet Pin Buffer Function Type Type I PD, Port 4 Receive Data Bit 2 ...
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Table 3 IO Signals (cont’d) Ball No. Name 106 P4_BUSMD0 MMII_P4TXD0 PMII_P4TXD0 105 P4_BUSMD1 MMII_P4TXD1 PMII_P4TXD1 103 MMII_P4TXD3 PMII_P4TXD3 104 MMII_P4TXD2 PMII_P4TXD2 Data Sheet Pin Buffer Function Type Type I PD, Port 4 Bus Type Configuration 0 LVTTL Value on ...
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Table 3 IO Signals (cont’d) Ball No. Name 114 MMII_P4TXEN PMII_P4TXEN 117 MMII_P4RXCLK I PMII_P4RXCLK O 115 MMII_P4TXCLK I PMII_P4TXCLK 62 P4FX Data Sheet Pin Buffer Function Type Type O 8 mA, Port 4 Transmit Enable in MAC MII Mode ...
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Table 3 IO Signals (cont’d) Ball No. Name Port 5 MII Interface 63 GFCEN MII_P5TXD0 GPSI_P5TXD RMII_P5TXD0 61 P5_BUSMD0 MII_P5TXD1 RMII_P5TXD1 Data Sheet Pin Buffer Function Type Type I PU, Global Flow Control Enable LVTTL Value on this pin will ...
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Table 3 IO Signals (cont’d) Ball No. Name 60 P5_BUSMD1 MII_P5TXD2 59 SDIO_MD MII_P5TXD3 66 PHYAS0 MII_P5TXEN GPSI_P5TXEN RMII_P5TXEN 53 MII_P5RXD0 GPSI_P5RXD RMII_P5RXD0 Data Sheet Pin Buffer Function Type Type I PD, Port 5 Bus Mode Selection Bit 1 LVTTL ...
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Table 3 IO Signals (cont’d) Ball No. Name 54 MII_P5RXD1 RMII_P5RXD1 55 MII_P5RXD2 56 MII_P5RXD3 52 MII_P5RXDV RMII_P5 CRSDV 68 MII_P5RXER RMII_P5RXER 57 MII_P5CRS GPSI_P5CRS 58 MII_P5COL GPSI_P5COL Data Sheet Pin Buffer Function Type Type I PD, Port 5 Receive ...
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Table 3 IO Signals (cont’d) Ball No. Name 72 MII_P5RXCLK GPSI_P5 RXCLK REFCLK_IN 67 MII_P5TXCLK GPSI_P5 TXCLK REFCLK _ OUT O 89 SPDTNP5 90 LNKFP5 91 DPHALFP5 LED Interface Data Sheet Pin Buffer Function Type Type I PD, Port 5 ...
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Table 3 IO Signals (cont’d) Ball No. Name 107 DPHALFP4 DUPCOL4 110 DUPCOL3 111 BPEN DUPCOL2 112 PHYAS1 DUPCOL1 Data Sheet Pin Buffer Function Type Type I PD, Port 4 Duplex status Input LVTTL When Port 4 operates under MAC ...
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Table 3 IO Signals (cont’d) Ball No. Name 113 RECANEN DUPCOL0 92 LNKFP4 LNKACT_4 95 LNKACT_3 96 LNKACT_2 97 LNKACT_1 98 LNKACT_0 51 SPDTNP4 LDSPD_4 48 LDSPD_3 47 LDSPD_2 43 LDSPD_1 42 LDSPD_0 EEPROM Interface Data Sheet Pin Buffer Function ...
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Table 3 IO Signals (cont’d) Ball No. Name 84 EDO 80 IFSEL EECS 81 XOVEN EESK SDC Data Sheet Pin Buffer Function Type Type I PU, EEPROM Data Output LVTTL This pin is used to input EEPROM data when reading ...
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Table 3 IO Signals (cont’d) Ball No. Name 79 LED_MODE EDI SDIO Power/Ground, 48 Pins 4, 5, 12, 13, GNDA 20, 27, 28, 34 17, 24, VCCA2 38 8, 16, 23, 31 VCCAD 126 GNDBIAS 128 VCCBIAS ...
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Table 3 IO Signals (cont’d) Ball No. Name 86 CFG0 69 WAIT_INIT 65 INT_N 40 MDIO 44 MDC 85 CKO25M 119 RC 120 XI 121 XO 127 RTX Data Sheet Pin Buffer Function Type Type I PU, Configuration 0 LVTTL ...
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Table 3 IO Signals (cont’d) Ball No. Name 125 VREF 124 CONTROL Data Sheet Pin Buffer Function Type Type AI ANA Analog Reference Voltage Used by Internal Bias Circuit for voltage reference. External 0.1uF capacitor connection to ground for noise ...
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Function Description 3.1 Switch Functional Description The Samurai-6M/6MX (ADM6996M/MX) uses the “store & forward” switching approach for the following reasons: 1. Store & forward switches allow switching between different speed media (e.g. 10BaseX and 100BaseX). Such switches require large ...
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After 16 consecutive retransmit trials, the Samurai-6M/6MX (ADM6996M/MX) resets the collision counter. Users can set the Back Off (see 0010 3.1.6 Inter-Packet Gap (IPG) IPG is the idle time between any two successive packets from the same port. The ...
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Samurai-6M/6MX (ADM6996M/MX) will treat it the storm has finished. 3.1.10 Bandwidth Control Samurai-6M/6MX (ADM6996M/MX) supports hardware-based bandwidth control for both ingress and egress traffic. Ingress and egress rate can be ...
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Table 6 Discard Ratio (cont’d) Discard Mode 00 Utilization 01 0% Utilization 11 0% 3.1.12 LED Display Three LEDs per port are provided by Samurai-6M/6MX (ADM6996M/MX): Link/Act, Duplex/Col and Speed. The dual-color LED mode is also supported by Samurai-6M/6MX (ADM6996M/MX). ...
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Table 7 Single Color LED Display (cont’d) Pin Name Status DUPCOL2/ These 3 pins have power on reset values on them. Samurai-6M/6MX (ADM6996M/MX) DUPCOL1/ needs to consider these values to drive the correct value. If the power on reset value ...
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Dual Color LED Display Users should be careful that DUPCOL LED only supports the single color mode. The only difference between single and dual color for DUPCOL LED is the self-test time. Table 8 Dual Color LED Display Pin ...
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Circuit for Dual LED Mode LDSPD4/LDSPD3/ LDSPD2/LDSPD1/ LDSPD0 Figure 4 Circuit for Dual Color LED Mode 3.1.13 Packet Identification Packets are classified to determine if they should be passed to the CPU port or another entity for special handling. ...
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Table 9 Packet Identification (cont’d) Packets Identified by Samurai- 6M/6MX (ADM6996M/MX) Others TYPE PROTOCOL TCPUDP MAC_CTRL For learning purpose, Samurai-6M/6MX (ADM6996M/MX) sometimes divides Ethernet address into three groups. Table 10 Packet Identification Groups Packets Identified by Samurai- 6M/6MX (ADM6996M/MX) MULTICAST ...
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Table 12 Management Packet Packet Type BPDU/SLOW/PAE/RESER_R0/ RESER_R1/GXRP/RESER_R2/ RESER_R3 ARP/RARP IGMP_IP/MLD_IP/MLD_IPV6 Others 3.1.13.3 Cross_VLAN Packet Cross-VLAN packets are defined to cross VLAN boundary or bypass the VLAN violation. Table 13 Cross_VLAN Packet Packet Type BPDU/SLOW/PAE/RESER_R0/ RESER_R1/GXRP/RESER_R2/ RESER_R3 ARP/RARP Data Sheet ...
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Table 13 Cross_VLAN Packet (cont’d) Packet Type IGMP_IP/MLD_IP/MLD_IPV6 Others 3.1.14 Tagged VLAN or Port VLAN The difference between two VLAN rules is the way to search the VLAN boundary. Users could enable “TAG Base VLAN” (see 0011 , TBV) bit ...
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VLAN Security Samurai-6M/6MX (ADM6996M/MX) ignores packet’s VID and always uses PVID to see if there is a match and transfers it to the output ports. Disables the “VLAN Security Disable” (See 0022 this goal. Input Force No Tag when enabled ...
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Table 17 VLAN Boundary Search Algorithm (cont’d) Tagged VID match Member is contained in the matched filter. We can find the boundary in this filter VLAN VID un- VID check match VID uncheck 3.1.14.8 Ingress Filter If the source port ...
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First Way: New Transmit Tag Disable (see 0x000ah) The “Output Packet Tagging” bit in the basic control registers determines the tagged members. Second Way: New Transmit Tag Enable (see 0x000ah) Port VLAN The source port number is the VLAN filter ...
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Table 19 Egress Tag Result (cont’d) Tagged packets are Output port is in the received. tagged members carried with the packet. Output port is not in the tagged members carried with the packet. Output port is configured to operate in ...
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Table 20 Tagged PRI Carried (cont’d) Tagged packets are Port VLAN [Change Priority Enable, Change Rule] (see 000A received. Tagged VLAN Reserve PRI is reversed from the priority queue the packet is switched through. Compare = queue, queue, queue, queue} ...
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Table 22 Priority Queue Queue Queue 0 Queue 1 Queue 2 Queue 3 3.1.15.1 System PRI The system PRI is determined in the order as follows: 1. (DA+FID) was found in the learning table, then LRN_PRI field (when LRN_PRIEN is ...
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Table 23 Queue Assigned (cont’d) Packets Identified by Samurai- 6M/6MX (ADM6996M/MX) IGMP_IP/MLD_IP/MLD_IPV6 Others Data Sheet The Order of Priority Assigned 1. The PRI field with PRI_Valid = 1 in the Special TAG indicates the priority queue. 2. Use PRI in ...
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Configure Samurai QoS Function Figure 5 To Configure Samurai QoS Function 3.1.16 Address Learning Samurai-6M/6MX (ADM6996M/MX) provides two ways to create the entry in the address table: dynamic learning and manual learning. A four-way hash algorithm is implemented to ...
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SSRAM. Samurai-6M/6MX (ADM6996M/MX) searches the learning table for the SA+FID of the incoming packet or the instruction from CPU. When both fields (a single SA may exist in different FID) are matched, there is a match. 3.1.16.1 ...
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Field Description Occupy The entry is marked to show the status if the entry is occupied. 0 Don’t occupy B 1 Occupy B Info_Ctrl/Age Timer Info_Ctrl is used when the entry is static. Bit 4:3 2 ...
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Table 24 Control Register Description for Accessing the Address Table Command Access Control Control 5[6:4] Control 5[3:0] The Address, FID, Portmap, Info_Ctrl/Age Timer and Info_Type in the Control Register have the same meaning as those in the entry format. The ...
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Table 27 Description for the Status Register (cont’d) Result This field tells us the status for not only the search operation but also the creating operation. 000 Command OK B 001 All Entry Used. This result happens only for the ...
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Example Example Rule The user needs Samurai- 1. Check the Busy bit. If Busy = 0 6M/6MX (ADM6996M/MX) 2. Write 789A to forward the specified 3. Write 3456 unicast packet (DA = 0012- 4. Write 0012 3456-789A and FID ...
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EEPROM register 00C bit [0], Hardware IGMP Default Router Enable EEPROM register 00D bit [14], IP Multicast Packet Treated as Cross VLAN packet EEPROM register 01B bit [14:9], Multicast Port-Map. H 10. EEPROM register 03F ...
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Table 30 Entry Format of IGMP Membership Table Busy Result Status 5[15] Status 5[14:12] 3.1.17.3 IGMP Snooping Introduction IGMP snooping is a feature that allows the switch to “listen in” on the IGMP conversation between hosts and routers. When a ...
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Table 32 IPV4/IGMP/V1 Report DA SA Type 01005exxxxxx 6 bytes 16’h0800 Unused TP Unused (Len*4-20) bytes 8’h12 3 bytes Host membership queries are sent by router to the all multicast address: 224.0.0.1. These queries use 0.0.0.0 in the IGMP GDA ...
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Group-specific Query a router can now send a group-specific query by sending a Membership Query to the group GDA instead of sending it to 0.0.0.0 Table 37 IPV4/IGMP/Group-Specific Query DA SA Type 01005exxxxxx 6 bytes 16’h0800 Unused TP Unused ...
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Table 38 IGMP Membership Table Address Table Control 0 EEPROM register 11A Address Table Control 1 EEPROM register 11B Address Table Control 2 EEPROM register 11C Address Table Control 3 EEPROM register 11D Address Table Control 4 EEPROM register 11E ...
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Security Mode Description First Lock Samurai-6M/6MX (ADM6996M/MX) locks the first SA+FID of packets received on the port. After the first (SA+FID) is locked, Samurai-6M/6MX (ADM6996M/MX) starts to check packets with different (SA+FID the packets are not assigned as ...
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Samurai-6M/6MX (ADM6996M/MX) supports stricter security protection. The port is disabled when there is a source violation. Enable Security Option[3] to enable this feature. 3.1.20 Packet Forwarding Samurai-6M/6MX (ADM6996M/MX) identifies packet headers and transfers it from the incoming port to the ...
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Table 39 Forwarding Algorithm (cont’d) Packets Identified by Samurai- 6M/6MX (ADM6996M/MX) IGMP_IP/MLD_IP/MLD_IPV6 TYPE PROTOCOL TCPUDP MAC_CTRL Others Data Sheet Algorithm IF (Portmap_Valid in the Special Tag is 1), THEN use Portmap in the Special Tag as the output ports. ELSE ...
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Special TAG Special Tag is inserted after the Ethernet SA field allows the CPU to tell the switch how to handle the packets it sends or to know the source port when the CPU receives a packet. 8 Bytes ...
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Table 40 Special Tag for the Receive (cont’d) Special TAG Byte 3 Byte 4 Byte 5 Data Sheet Description Bit [7]: Span_Valid 1 Valid B 0 Not Valid B Bit [6]: Span 1 Span packet B 0 Not span packet ...
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Special Tag for the Transmit Users are allowed to enable Special TAG Transmit (0011 (ADM6996M/MX) to insert the Special Tag followed SA in the packets transmitted from the CPU port. Samurai- 6M/6MX (ADM6996M/MX) also allows users to choose what ...
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Table 41 Option for Special Tag Transmit (cont’d) Packets Identified by Samurai- 6M/6MX (ADM6996M/MX) Others Table 42 Special Tag for the Transmit Special TAG Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Data Sheet Condition Special ...
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Port4 and Port5 MII Connection In ADM6996M/MX, there are 3 different configurations (Normal PHY, MAC type MII and PCS type MII, CFG0) for Port4. If Port4 is configured in normal PHY mode, then it is identical to Port0~Port3 and ...
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Step 1: Set EEPROM 11 [12]=1 to enable Special TAG Receive (CPU to ADM6996M/MX). H Step 2: Set EEPROM 11 [11]=1 to enable Special TAG Transmit (ADM6996M/MX to CPU). H Set EEPROM 11 [15:13] to assign CPU Port Number. Default ...
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Step 3: Set EEPROM 11 [12:11]="11" to enable Special TAG Receive/Transmit Enable H Software Operation: Figure 8 Software Operation • Step 1: – If Untag packet received from LAN Port forwards to CPU Port, ADM6996M/MX will insert Special TAG ...
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Table 45 Packets Identified by ADM6996M/MX (cont’d) Packets Identified by Condition ADM6996M/MX (EEPROM 0x11h[11] and 0x99h[8:0] TYPE Special TAG Transmit = 0 {Special TAG Transmit, Insert Type {Special TAG Transmit, Insert Type PROTOCOL Special TAG Transmit ...
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P0 MAC P0 PHY Figure 9 ADM6996M/MX to CPU with dual MII Connection Normally, the MAC mode MII should be connected to the PHY mode MII. But in some applications, we need to connect both MAC mode MII to each ...
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P5_BUSMD1 (60) P5_BUSMD0 (61) SPDTNP5 (89) Note DPHALFP5 (91) LNKFP5 (90) Figure 10 100M Full duplex MAC to MAC MII Connection Note: 1. Pin 60 and pin 61 should be pull low to let P5_BUSMD be latched as “00” and ...
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Figure 11 PCS to MAC MII connection Note: 5. From the CFG0 pin description, we know it needs to set {CFG0, P4_BUSMD[1:0]} as 1xx be operating in PCS mode MII doesn’t matter the value on P4_BUSMD[1:0] (pin 105 ...
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Auto Negotiation The Auto Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. Fast Link Pulse (FLP) Bursts provide ...
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These pins are also used for evaluating the default value in the base H mode control register (register 0 In order to make these pins have the same Read/Write priority as software, they ...
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Table 47 Hardware Setting Setting Name GFCEN SDIO_MD P5_BUSMD[1:0] {CFG0, P4_BUSMD[1:0]} BPEN RECANEN XOVEN LED_MODE 3.4.2 EEPROM Interface The EEPROM Interface is provided to easily configure the setting without the CPU’s help. Because the EEPROM Interface is the same as ...
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READ command. If the CPU sends out the Read Command, then 93c66 will respond with the value inside, instead of Samurai-6M/6MX (ADM6996M/MX). Users should also note that one additional EESK cycle is needed between any ...
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Figure 13 The Power-On-Sequence of Samurai Set ADM6996LC/FC Pin59 SDIO_MD=1 to 16-bit SMI mode. Set ADM6996I/M Pin59 SDIO_MD=0(default) to 16-bit SMI mode. Timing Diagram of RC, EECS and EESK (with correct signature EEPROM) Waveform 1: RC Reset Waveform 2: EECS ...
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Figure 14 Timing Diagram of RC, EECS and EESK (with correct signature EEPROM) Timing Diagram of RC, EECS and EESK (without EEPROM) Waveform 1: RC Reset Waveform 2: EECS Waveform 4: EESK Data Sheet 76 Samurai-6M/MX ADM6996M/MX Function Description Revision ...
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Figure 15 Timing Diagram of RC, EECS and EESK (without EEPROM) 3.4.3 SMI Interface The SMI consists of two pins, management data clock (EESK) and management data input/output (EDI). The Samurai-6M/6MX (ADM6996M/MX) is designed to support an EESK frequency up ...
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When Samurai-6M/6MX (ADM6996M/MX) detects that there is address match, then it will enable Read/Write capability for external access. When address is mismatched, then Samurai-6M/6MX (ADM6996M/MX) will tristate the EDI pin. (B) Read Switch Register via SMI Interface (Offset Hex = ...
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Memory Map Table 49 Memory Map Register 0000 ~ 003F H H 0040 ~ 009B H H 00A0 ~ 0143 H H 0200 ~ 02FF you need to divide 10-bit register address to 5-bit PHY address and ...
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Registers Description The EEPROM provides Samurai-6M/6MX (ADM6996M/MX) with many option settings Main Settings • Port Configuration: Speed, Duplex, Flow Control Capability and Tag/ Untag. • VLAN & TOS Priority Mapping • Broadcast Storming rate and Trunk. • Fiber Select, ...
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Table 52 Registers Overview (cont’d) Register Short Name Register Long Name SC4 System Control Register 4 P0SO Port 0 Security Option P1SO Port 1 Security Option P2SO Port 2 Security Option P3SO Port 3 Security Option P4SO Port 4 Security ...
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Table 52 Registers Overview (cont’d) Register Short Name Register Long Name EBC1 Extended Bandwidth Control Register 1 EBC2 Extended Bandwidth Control Register 2 EBC3 Extended Bandwidth Control Register 3 EBC4 Extended Bandwidth Control Register 4 EBC5 Extended Bandwidth Control Register ...
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Table 52 Registers Overview (cont’d) Register Short Name Register Long Name VF14H VLAN Filter 14 High VF15L VLAN Filter 15 Low VF15H VLAN Filter 15 High TF0 Type Filter 0 TF1 Type Filter 1 TF2 Type Filter 2 TF3 Type ...
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Table 52 Registers Overview (cont’d) Register Short Name Register Long Name RA_13_12 Reserve Action for 0180C2000013~0180C2000012 RA_15_14 Reserve Action for 0180C2000015~0180C2000014 RA_17_16 Reserve Action for 0180C2000017~0180C2000016 RA_19_18 Reserve Action for 0180C2000019~0180C2000018 RA_1B_1A Reserve Action for 0180C200001B~0180C200001A RA_1D_1C Reserve Action for ...
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Table 52 Registers Overview (cont’d) Register Short Name Register Long Name EICSTIC Extended IGMP Control/Special Tag Insert Control 99 IE Interrupt Enable Register IS Interrupt Status Register SC Security Control Register CI0 Chip Identifier 0 CI1 Chip Identifier 1 PS0 ...
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Table 52 Registers Overview (cont’d) Register Short Name Register Long Name CH14 Port 2 Transmit Packet Count High CL15 Port 3 Transmit Packet Count Low CH15 Port 3 Transmit Packet Count High CL16 Port 4 Transmit Packet Count Low CH16 ...
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Table 52 Registers Overview (cont’d) Register Short Name Register Long Name CL35 Port 5 Error Count Low CH35 Port 5 Error Count High OFF0 Over-Flow Flag 0 OFF1 Over-Flow Flag 1 OFF2 Over-Flow Flag 2 OFF3 Over-Flow Flag 3 OFF4 ...
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Table 52 Registers Overview (cont’d) Register Short Name Register Long Name PHY_I1_B PHY Identifier Register of Port 1 (B) ANAP1 Auto Negotiation Advertisement Register of Port 1 224 ANLPA1 Auto Negotiation Link Partner Ability Register of Port 1 ANE1 Auto ...
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Table 53 Register Access Types Mode Symbol Description HW read/write rw Register is used as input for the HW read r Register is written by HW (register between input and output -> one cycle delay) Read only ro Register is ...
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EEPROM Basic Registers Signature Register SIG Signature Register Field Bits Type SIG 15 Basic Control Register P0BC P0 Basic Control Register Data Sheet Offset 00 H Description Signature The value must be 4154 . Samurai-6M/6MX (ADM6996M/MX) uses ...
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Field Bits Type CROSS_EE 15 rw SELFX_EE 14 rw PVID3_0 13: 9:8 rw PPE 7 rw IPVLAN OPTE Data Sheet Description Crossover Auto Detect Enable This bit is ...
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Field Bits Type ANE 1 rw FCE 0 rw Similar Registers Table 55 P1~P5 Basic Control Registers Register Short Name Register Long Name P1BC P1 Basic Control Register P2BC P2 Basic Control Register P3BC P3 Basic Control ...
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Field Bits Type LD135 13 rw MNA135 12:8 rw Res 7 r AD024 6 rw LD024 5 rw MNA024 4:0 rw Similar Registers Table 56 Px_EC Registers Register Short Name Register Long Name P1EC P1 Extended Control Register P2EC P2 ...
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Field Bits Type ERCMPTH 15:12 rw PCR 11 rw PCE 10 rw RVID0 9 rw RVID1 8 rw RVIDFFF 7 rw DFID 6:3 rw NTTE System Control Register 1 SC1 System Control ...
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Field Bits Type DFEFD ASC 13:12 rw SIC 11 rw SIM 10 rw SIA 9 rw CMS TSIE 6 rw Data Sheet Description Disable Far-End-Fault Detection 0 Far-End-Fault detect ion ...
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Field Bits Type CPDC 5 rw SVOR 4 rw SVOA 3 rw SVOS 2 rw SVOD Multicast Snooping Register MS Multicast Snooping Register Data Sheet Description CPU Port Doesn’ t Check CPU Port doesn’ t ...
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Field Bits Type SCPA 15:14 rw SCPPE 13 rw SCPP 12:11 rw SCPTTH 10:9 rw SCPTC 8 rw SCPTM 7 rw SCPTS 6 rw TMI6P 5 rw TMIP 4 rw TIP 3 rw HIPI 2 rw Data Sheet Description Snooping ...
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Field Bits Type HISE 1 rw HIDRE 0 rw Data Sheet Description Hardware IGMP Snooping Enable 0 Disable Hardware IGMP Snooping B 1 Enable Hardware IGMP Snooping B Hardware IGMP Default Router Enable 0 Disable B 1 Enable B 98 ...
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ARP/RARP Register AR ARP/RARP Register Field Bits Type Res 15 r IMP 14 rw UPT 13 rw RPT 12 rw RAPA 11:10 rw RAPPE 9 rw RAPP 8:7 rw Data Sheet Offset 0D H Description Reserved IP Multicast Packet Treated ...
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Field Bits Type RAPOTH 6:5 rw APT 4 rw RAPTM 3 rw TAPTS 2 rw TAP 1 rw TRP 0 rw VLAN Priority Map Register VPM VLAN Priority Map Register Field Bits Type PQ7 15:14 rw PQ6 13:12 rw Data ...
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Field Bits Type PQ5 11:10 rw PQ4 9:8 rw PQ3 7:6 rw PQ2 5:4 rw PQ1 3:2 rw PQ0 1:0 rw TOS Priority Map Register TPM TOS Priority Map Register Field Bits Type PQ7 15:14 rw PQ6 13:12 rw PQ5 ...
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Field Bits Type PQ4 9:8 rw PQ3 7:6 rw PQ2 5:4 rw PQ1 3:2 rw PQ0 1:0 rw System Control Register 2 SC2 System Control Register 2 Field Bits Type DM_Q3 15:14 rw DM_Q2 13:12 rw DM_Q1 11:10 rw DM_Q0 ...
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Field Bits Type CCD 1:0 rw System Control Register 3 SC3 System Control Register 3 Field Bits Type CPN 15:13 rw Data Sheet Description Rx ...
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Field Bits Type STRE 12 rw STTE MPL 9:7 rw NSE 6 rw TBV 5 rw MCE IPI 2 rw ATS 1:0 rw System Control Register 4 SC4 System Control ...
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Field Bits Type DUP_COL_SE Res 13:12 rw TLE 11 rw Res 10 rw Res 9 rw O5FL 8 rw O4FL 7 rw O3FL O2FL 4 rw DUAL ...
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Field Bits Type O1FL 2 rw LED-ENABLE 1 rw O0FL 0 rw Port 0 Security Option Port Spanning Tree State and Forward Group Port Map. P0SO Port 0 Security Option Field Bits Type Res PSO ...
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Field Bits Type STPS 10 Res Res Res Similar Registers Table 57 PxSO Registers Register ...
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Unicast Port Map and Forward Group Port Map UFGPM Unicast Port Map andForward Group Port Map Field Bits Type Res 14 Res ...
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Field Bits Type Res 14 Res Res Res Multicast Port Map and ...
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Field Bits Type Res 14 Res Res Res Reserve Port Map and ...
Page 111
Field Bits Type Res Res Res Packet Identification Option, Forward Group Port Map PIOFGPM Packet Identification ...
Page 112
Field Bits Type DIIPS 12 rw DIE 11 rw DIIP 10 rw DIS Res Res Res ...
Page 113
Field Bits Type Res 15 r VPE 14 Res Res Res Service Priority Enable and ...
Page 114
Field Bits Type SPE 14 Res Res Res Input Force No Tag and Forward Group ...
Page 115
Field Bits Type Res Res Res Ingress Filter andForward Group Port Map IFFGPM Ingress Filter andForward ...
Page 116
Field Bits Type Res Res Res VLAN Security Disable and Forward Group Port Map VSDFGPM VLAN Security Disable and Forward Group Port ...
Page 117
Field Bits Type Res Res Data Sheet Description Port member of the Forwarding Group 0 Port 2 is not a member B 1 Port ...
Page 118
Buffer Threshold Register 0 BT0 Buffer Threshold Register 0 Field Bits Type Res 15:0 r Buffer Threshold Register 1 BT1 Buffer Threshold Register 1 Field Bits Type Res 15:0 r IGMP/MLDTRAP Enable and Input Jam Threshold Register IMEIJT IGMP/MLDTRAP Enable ...
Page 119
Field Bits Type Q1W 15:12 rw IMTE 11:6 rw IJT 5:0 rw Queue 2 Weight, VID Exist Check, and PPPOE Port Only Q2WVECPO Queue 2 Weight, VID Exist Check, and PPPOE Port Only Field Bits Type Q2W 15: ...
Page 120
Field Bits Type Q3W 15:12 rw BPV 11:6 rw AOVTP 5:0 rw Input Double Tag Enable, and P0VID[11:4] IDTEP Input Double Tag Enable, and P0VID[11:4] Field Bits Type Res 15:14 rw Res 13:8 rw P0VID_11_4 7:0 rw Output Double Tag ...
Page 121
Field Bits Type Res 15:14 rw Res 13:12 rw Res 11 rw BCTS 10:9 rw BPM 8 rw P1VID_11_4 7:0 rw Output Tag Bypass, and P2VID[11:4] OTBP Output Tag Bypass, and P2VID[11:4] Field Bits Type Res 15:14 rw OTBE 13:8 ...
Page 122
P11_4 P3VID[11:4], and P4VID[11:4] Field Bits Type P4VID_11_4 15:8 rw P3VID_11_4 7:0 rw Reserved Address Control, and P5VID[11:4] RACP Reserved Address Control, and P5VID[11:4] Field Bits Type AMA3 15 rw AMA2 14 rw AMA1 13 rw AMA0 12 rw TAG_SHIFT ...
Page 123
PHYC PHY Control Register Field Bits Type CICD 15 rw Res 14 rw Res 13 rw Res 12:11 rw Res 10 rw Res 9 rw Res 8 rw Res 7 rw Res 6 rw Res 5 rw Res 4 rw ...
Page 124
Field Bits Type ATET 15:0 rw PHY Restart Register PR PHY Restart Register Field Bits Type RESTART 15:0 rw Miscellaneous Register MISC Miscellaneous Register Field Bits Type Res 15 rw Res 14 rw Res 13 rw Data Sheet Description ADM ...
Page 125
Field Bits Type Res 11 rw Res 10 rw DHCOL_LED_ Res 6 rw MCEB 5 rw Res 4 rw Res 3 rw Res 2 rw Res 1 rw ...
Page 126
Field Bits Type R2BW_TH1 11 rw R2BW_TH0 10:8 rw R1BW_TH1 7 rw R1BW_TH0 6:4 rw R0BW_TH1 3 rw R0BW_TH0 2:0 rw Basic Bandwidth Control Register 1 BBC1 Basic Bandwidth Control Register 1 Field Bits Type T1BW_TH1 15 rw T1BW_TH0 14:12 ...
Page 127
Bandwidth Control Enable Register BCE Bandwidth Control Enable Register Field Bits Type IPCP 15 rw CLC 14 rw Res 13 rw ANBCE 12 rw P5TBCE 11 rw P4TBCE 10 rw P3TBCE 9 rw P5RBCE 8 rw Data Sheet Offset 33 ...
Page 128
Field Bits Type P4RBCE 7 rw P3RBCE 6 rw P2TBCE 5 rw P2RBCE 4 rw P1TBCE 3 rw P1RBCE 2 rw P0TBCE 1 rw P0RBCE 0 rw Extended Bandwidth Control Register 0 EBC0 Extended Bandwidth Control Register 0 Data Sheet ...
Page 129
Field Bits Type T5BW_TH1 15 rw T5BW_TH0 14:12 rw T4BW_TH1 11 rw T4BW_TH0 10:8 rw T3BW_TH1 7 rw T3BW_TH0 6:4 rw T2BW_TH1 3 rw T2BW_TH0 2:0 rw Extended Bandwidth Control Register 1 EBC1 Extended Bandwidth Control Register 1 Field Bits ...
Page 130
Field Bits Type R0BW_TH2 3:0 rw Extended Bandwidth Control Register 2 EBC2 Extended Bandwidth Control Register 2 Field Bits Type T1BW_TH2 15:12 rw T0BW_TH2 11:8 rw R5BW_TH2 7:4 rw R4BW_TH2 3:0 rw Data Sheet Description Port 0 Receive Bandwidth Maximum[7:4]. ...
Page 131
Extended Bandwidth Control Register 3 EBC3 Extended Bandwidth Control Register 3 Field Bits Type T5BW_TH2 15:12 rw T4BW_TH2 11:8 rw T3BW_TH2 7:4 rw T2BW_TH2 3:0 rw Extended Bandwidth Control Register 4 EBC4 Extended Bandwidth Control Register 4 Field Bits Type ...
Page 132
Field Bits Type R3BW_TH3 11:9 rw R2BW_TH3 8:6 rw R1BW_TH3 5:3 rw R0BW_TH3 2:0 rw Extended Bandwidth Control Register 5 EBC5 Extended Bandwidth Control Register 5 Field Bits Type FMDIX1 15 r T3BW_TH3 14:12 rw T2BW_TH3 11:9 rw T1BW_TH3 8:6 ...
Page 133
DVMEBC6 Default VLAN Member and Extended Bandwidth Control Register 6 Field Bits Type Res 15:12 rw DVM 11:6 rw T5BW_TH3 5:3 rw T4BW_TH3 2:0 rw New Storm Register 0 NS0 New Storm Register 0 Field Bits Type Res 15 r ...
Page 134
Field Bits Type STORM_100_ 12 Data Sheet Description 100M Threshold See Chapter 3.1.9 Broadcast Storm used when all ports link up in the 100M. The upper bound is reached when the number of the packets received during the ...
Page 135
New Storm Register 1 NS1 New Storm Register 1 Field Bits Type FMDIX4 15 rw FMDIX3 14 rw FMDIX2 13 rw STORM_10_T 12 New Reserve Address Control Register 0 NRAC0 New Reserve Address Control Register 0 Data Sheet ...
Page 136
Field Bits Type NRTB 15: 13:12 rw PRI_S 11:10 rw PRI_B 9:8 rw R3PP 7 rw R2PP 6 rw GPP 5 rw R1PP 4 rw R0PP 3 rw PPP 2 rw Data Sheet Description New Reserve TXTAG for ...
Page 137
Field Bits Type SPP 1 rw BPP 0 rw New Reserve Address Control Register 1 NRAC1 New Reserve Address Control Register 1 Field Bits Type MCA1 15 rw MCA2 14:13 rw NRMG 12 rw NRMS 11 rw MRMB 10 rw ...
Page 138
Field Bits Type NRSS 8 rw NRSB 7 rw NRCG 6 rw NRCS 5 rw NRCB 4 rw NRTG 3:2 rw NRTS 1:0 rw Hardware IGMP Control Register HIC Hardware IGMP Control Register Data Sheet Description New Reserve Span for ...
Page 139
Field Bits Type QI 15 7:6 rw DRP 5:0 rw 4.2 EEPROM Extended Registers VLAN Filter 0 Low VF0L VLAN Filter 0 Low Field Bits Type FID 15: 11:6 rw Data Sheet Description Query Interval The ...
Page 140
Field Bits Type M 5:0 rw Similar Registers Table 58 VFxL Registers Register Short Name Register Long Name VF1L VLAN Filter 1 Low VF2L VLAN Filter 2 Low VF3L VLAN Filter 3Low VF4L VLAN Filter 4 Low VF5L VLAN Filter ...
Page 141
Field Bits Type VP 14:12 rw VID 11:0 rw Similar Registers All VFxH registers have the same structure and characteristics, see VF0H. The offset addresses of the other VFxH registers are listed in Table 59 VFxH Registers Register Short Name ...
Page 142
Similar Registers All TFx registers have the same structure and characteristics, see TF0. The offset addresses of the other TFx registers are listed in Table 60 TFx Registers Register Short Name Register Long Name TF1 Type Filter 1 TF2 Type ...
Page 143
Protocol Filter 1 and 0 PF_1_0 Protocol Filter 1 and 0 Field Bits Type PFR1 15:8 rw PFR0 7:0 rw Similar Registers All PFx registers have the same structure and characteristics, see PF_1_0. The offset addresses of the other PFx ...
Page 144
Field Bits Type PQ6 13:12 rw PQ5 11:10 rw PQ4 9:8 rw PQ3 7:6 rw PQ2 5:4 rw PQ1 3:2 rw PQ0 1:0 rw Service Priority Mapping 1 SPM1 Service Priority Mapping 1 Field Bits Type PQF 15:14 rw PQE ...
Page 145
Field Bits Type PQD 11:10 rw PQC 9:8 rw PQB 7:6 rw PQA 5:4 rw PQ9 3:2 rw PQ8 1:0 rw Service Priority Mapping 2 SPM2 Service Priority Mapping 2 Field Bits Type PQ17 15:14 rw PQ16 13:12 rw PQ15 ...
Page 146
Field Bits Type PQ13 7:6 rw PQ12 5:4 rw PQ11 3:2 rw PQ10 1:0 rw Service Priority Mapping 3 SPM3 Service Priority Mapping 3 Field Bits Type PQ1F 15:14 rw PQ1E 13:12 rw PQ1D 11:10 rw PQ1C 9:8 rw PQ1B ...
Page 147
Field Bits Type PQ19 3:2 rw PQ18 1:0 rw Service Priority Mapping 4 SPM4 Service Priority Mapping 4 Field Bits Type PQ27 15:14 rw PQ26 13:12 rw PQ25 11:10 rw PQ24 9:8 rw PQ23 7:6 rw PQ22 5:4 rw PQ21 ...
Page 148
Service Priority Mapping 5 SPM5 Service Priority Mapping 5 Field Bits Type PQ2F 15:14 rw PQ2E 13:12 rw PQ2D 11:10 rw PQ2C 9:8 rw PQ2B 7:6 rw PQ2A 5:4 rw PQ29 3:2 rw PQ28 1:0 rw Service Priority Mapping 6 ...
Page 149
Field Bits Type PQ37 15:14 rw PQ36 13:12 rw PQ35 11:10 rw PQ34 9:8 rw PQ33 7:6 rw PQ32 5:4 rw PQ31 3:2 rw PQ30 1:0 rw Service Priority Mapping 7 SPM7 Service Priority Mapping 7 Data Sheet Description Priority ...
Page 150
Field Bits Type PQ3F 15:14 rw PQ3E 13:12 rw PQ3D 11:10 rw PQ3C 9:8 rw PQ3B 7:6 rw PQ3A 5:4 rw PQ39 3:2 rw PQ38 1:0 rw Reserve Action for 0180C2000001~0180C2000000 RA_01_00 Reserve Action for 0180C2000001~0180C2000000 Field Bits Type RA01_VALID ...
Page 151
Field Bits Type RA01_SPAN 14 rw RA01_MG 13 rw RA01_CV 12 rw RA01_TXTAG 11:10 rw RA01_ACT 9:8 rw RA00_VALID 7 rw RA00_SPAN 6 rw RA00_MG 5 rw RA00_CV 4 rw RA00_TXTAG 3:2 rw RA00_ACT 1:0 rw Data Sheet Description Span ...
Page 152
Similar Registers All RAx registers have the same structure and characteristics, see RA_01_00. The offset addresses of the other RAx registers are listed in Table 62 RAx Registers Register Short Name Register Long Name RA_03_02 Reserve Action for 0180C2000003~0180C2000002 RA_05_04 ...
Page 153
Table 62 RAx Registers (cont’d) Register Short Name Register Long Name RA_2B_2A Reserve Action for 0180C200002B~0180C200002A RA_2D_2C Reserve Action for 0180C200002D~0180C200002C RA_2F_2E Reserve Action for 0180C200002F~0180C200002E TCP/UDP Filter 0 TUF0 TCP/UDP Filter 0 Field Bits Type VAL_COMP 15:0 rw Similar ...
Page 154
Field Bits Type ATF7 15:14 rw ATF6 13:12 rw ATF5 11:10 rw ATF4 9:8 rw ATF3 7:6 rw ATF2 5:4 rw ATF1 3:2 rw ATF0 1:0 rw Protocol Filter Action PFA Protocol Filter Action Field Bits Type APF7 15:14 rw ...
Page 155
Field Bits Type APF6 13:12 rw APF5 11:10 rw APF4 9:8 rw APF3 7:6 rw APF2 5:4 rw APF1 3:2 rw APF0 1:0 rw TCP/UDP Action 0 TUA0 TCP/UDP Action 0 Field Bits Type ATUF3 15:14 rw TUPF3 13:12 rw ...
Page 156
Field Bits Type TUPF1 5:4 rw ATUF0 3:2 rw TUPF0 1:0 rw TCP/UDP Action 1 TUA1 TCP/UDP Action 1 Field Bits Type ATUF7 15:14 rw TUPF7 13:12 rw ATUF6 11:10 rw TUPF6 9:8 rw ATUF5 7:6 rw TUPF5 5:4 rw ...
Page 157
TCP/UDP Action 2 TUA2 TCP/UDP Action 2 Field Bits Type Res 15:14 r COMP 13:12 rw P5I 11 rw P4I 10 rw P3I 9 rw P2I 8 rw P1I 7 rw P0I 6 rw P5T 5 rw P4T 4 rw ...
Page 158
Field Bits Type P2T 2 rw P1T 1 rw P0T 0 rw Extended IGMP Control/Special Tag Insert Control EICSTIC Extended IGMP Control/Special Tag Insert Control Field Bits Type Res 15:10 rw IAC 9 rw INS_IP 8 rw INS_RES 7 rw ...
Page 159
Field Bits Type INS_PROT 3 rw INS_TU 2 rw INS_MC 1 rw INS_DEF 0 rw Interrupt Enable Register IE Interrupt Enable Register Field Bits Type Res 15:9 r LTADIE 8 rw PSIE 7:2 rw COIE 1 rw PSIE 0 rw ...
Page 160
Interrupt Status Register IS Interrupt Status Register Field Bits Type Res 15:9 r LTAD 8 lhsc PSV 7:2 lhsc CO 1 lhsc PSC 0 lhsc Security Control Register SC Security Control Register Field Bits Type Res 15:13 r Res 12:0 ...
Page 161
Counter and Switch Status Registers Chip Identifier 0 CI0 Chip Identifier 0 Field Bits Type PC 15 3:0 ro Chip Identifier 1 CI1 Chip Identifier 1 Field Bits Type Res 15 3:0 ro Port Status ...
Page 162
Field Bits Type Res 15:12 ro P1FCS 11 ro P1DS 10 ro P1SS 9 ro P1LS 8 ro Res 7:4 ro P0FCS 3 ro P0DS 2 ro P0SS 1 ro P0LS 0 ro Port Status 1 PS1 Port Status 1 ...
Page 163
Field Bits Type P4FCS 15 ro P4DS 14 ro P4SS 13 ro P4LS 12 ro P3FCS 11 ro P3DS 10 ro P3SS 9 ro P3LS 8 ro Res 7:4 ro P2FCS 3 ro P2DS 2 ro P2SS 1 ro P2LS ...
Page 164
Field Bits Type Res 15:5 ro P5FCE 4 ro P5DS 3 ro Res 2 ro P5SS 1 ro P5LS 0 ro Port Status 3 PS3 Port Status 3 Field Bits Type Res 15:0 r Cable Broken 0 CB0 Cable Broken ...
Page 165
Field Bits Type CB0 15:0 ro Cable Broken 1 CB1 Cable Broken 1 Field Bits Type CB1 15:0 ro Counter Low 0 CL0 Port 0 Receive Packet Counter Low Field Bits Type COUNTER 15:0 rw Similar Registers All CLx registers ...
Page 166
Table 64 CLx Registers Register Short Name Register Long Name CL1 Port 1 Receive Packet Counter Low CL2 Port 2 Receive Packet Counter Low CL3 Port 3 Receive Packet Counter Low CL4 Port 4 Receive Packet Counter Low CL5 Port ...
Page 167
Field Bits Type COUNTER 15:0 rw Similar Registers All CHx registers have the same structure and characteristics, see CH0. The offset addresses of the other CLH registers are listed in Table 65 CHx Registers Register Short Name Register Long Name ...
Page 168
Table 65 CHx Registers (cont’d) Register Short Name Register Long Name CH29 Port 5 Collision Count High CH30 Port 0 Error Count High CH31 Port 1 Error Count High CH32 Port 2 Error Count High CH33 Port 3 Error Count ...
Page 169
Field Bits Type P3_C 6 lhsc Res 5 ro P2_C 4 lhsc Res 3 ro P1_C 2 lhsc Res 1 ro P0_C 0 lhsc Over-Flow Flag 1 OFF1 Over-Flow Flag 1 Field Bits Type Res 15:2 ro P5_BC 1 lhsc ...
Page 170
Field Bits Type P3_BC 15 lhsc Res 14 ro P2_BC 13 lhsc Res 12 ro P1_BC 11 lhsc Res 10 ro P0_BC 9 lhsc P5_C 8 lhsc P4_C 7 lhsc P3_C 6 lhsc Res 5 ro P2_C 4 lhsc Res ...
Page 171
OFF3 Over-Flow Flag 3 Field Bits Type Res 15:2 ro P5_BC 1 lhsc P4_BC 0 lhsc Over-Flow Flag 4 OFF4 Over-Flow Flag 4 Field Bits Type P3EC 15 lhsc Res 14 ro P2EC 13 lhsc Res 12 ro P1EC 11 ...
Page 172
Field Bits Type P0EC 9 lhsc P5CC 8 lhsc P4CC 7 lhsc P3CC 6 lhsc Res 5 ro P2CC 4 lhsc Res 3 ro P1CC 2 lhsc Res 1 ro P0CC 0 lhsc Over-Flow Flag 5 OFF5 Over-Flow Flag 5 ...
Page 173
Hardware Setting Low Register HSL Hardware Setting Low Register Field Bits Type DAF P4IT 8:7 ro GFC 6 ro P4FM ...
Page 174
Field Bits Type LTBR 9 ro LLTBR 8 ro CTBR 7 ro HITBR 6 ro DBBR 5 ro P5M 4:3 ro P4M 2:1 ro CFG 0 ro Assign Address [15:0] Register AA1 Assign Address [15:0] Register Field Bits Type ASS_ADDR ...
Page 175
AA2 Assign Address [31:16] Register Field Bits Type ASS_ADDR 15:0 rw Data Sheet Offset 133 H Description Assign Address [31:16] 175 Samurai-6M/MX ADM6996M/MX Registers Description Reset Value 0000 H Revision 1.4, 2006-03-24 ...
Page 176
Assign Address [47:32] Register AA3 Assign Address [47:32] Register Field Bits Type ASS_ADDR 15:0 rw Assign Option Register AO Assign Option Register Field Bits Type Res 15:10 r PAC 9 rw Data Sheet Offset 134 H Description Assign Address [47:32] ...
Page 177
Field Bits Type AAO 8 6 2:0 rw Mirror Register 0 MIRR0 Mirror Register 0 Field Bits Type P3TM 15:14 rw P3RM 13:12 rw P2TM 11:10 rw P2RM 9:8 rw P1TM 7:6 rw P1RM 5:4 rw ...
Page 178
Field Bits Type P0RM 1:0 rw Mirror Register 1 MIRR1 Mirror Register 1 Field Bits Type MCA 14 rw MRA 13 rw MPA 12 rw MLA 11 rw MSA 10 rw Res 9 rw ETUP 8 rw ...
Page 179
Field Bits Type P5RM 5:4 rw P4TM 3:2 rw P4RM 1:0 rw Security Violation Port SVP Security Violation Port Field Bits Type Res 15:12 r PSI 11:6 rc Res 5:0 r Security Status 0 SS0 Security Status 0 Field Bits ...
Page 180
Field Bits Type PL 5:0 r Security Status 1 SS1 Security Status 1 Field Bits Type Res 15 5:0 r First Lock Address Search FLAS First Lock Address Search Field Bits Type Res 15:3 r Data Sheet Description ...
Page 181
Field Bits Type FLSP 2:0 rw Data Sheet Description First Lock Search Port Users could write this register to get the lock address and the lock FID (returned in the 13C , 13D , 13E H H 000 Search the ...
Page 182
First Lock Address [15:0] FLA1 First Lock Address [15:0] Field Bits Type FLA 15:0 r First Lock Address [31:16] FLA2 First Lock Address [31:16] Field Bits Type FLA 15:0 r First Lock Address [47:32] FLA3 First Lock Address [47:32] Data ...
Page 183
Field Bits Type FLA 15:0 r First Lock FID FLF First Lock FID Field Bits Type Res 15:4 r FLF 3:0 r Counter Control Low Register CCL Counter Control Low Register Field Bits Type Res 15:8 r BAS 7 rw ...
Page 184
Field Bits Type IRC_RPC 5:0 rw Data Sheet Description Indirect Read Counter It means the counter address Renew Port Counter It means the counters on each port to renew 184 Samurai-6M/MX ADM6996M/MX Registers Description Revision 1.4, 2006-03-24 ...
Page 185
Counter Control High Register CCH Counter Control High Register Field Bits Type Res 15:0 r Counter Status Low Register CSL Counter Status Low Register Field Bits Type COUNTER 15:0 r Counter Status High Register CSH Counter Status High Register Data ...
Page 186
Field Bits Type COUNTER 15:0 r 4.4 PHY Registers PHY Control Register of Port 0 PHY_C0 PHY Control Register of Port 0 Field Bits Type RST 15 rw, sc LPBK 14 rw SPEED_LSB 13 rw Data Sheet Description Counter [31:16] ...
Page 187
Field Bits Type ANEN 12 rw PDN 11 rw ISO 10 rw ANEN_RST 9 rw, sc DPLX 8 rw COLTST 7 rw SPEED_MSB 6 ro Similar Registers All PHY_Cx registers have the same structure and characteristics, see PHY_C0. The offset ...
Page 188
Table 66 PHY_Cx Registers Register Short Name Register Long Name PHY_C1 PHY Control Register of Port 1 PHY_C2 PHY Control Register of Port 2 PHY_C3 PHY Control Register of Port 3 PHY_C4 PHY Control Register of Port 4 Data Sheet ...
Page 189
PHY Status Register of Port 0 PHY_S0 PHY Status Register of Port 0 Field Bits Type CAP_T4 15 ro CAP_TXF 14 ro CAP_TXH 13 ro CAP_TF 12 ro CAP_TH 11 ro CAP_T2 10 ro CAP_SUPR 6 ro AN_COMP 5 ro ...
Page 190
Field Bits Type REM_FLT 4 ro CAP_ANEG 3 ro LINK 2 ro JAB 1 ro EXTREG 0 ro Similar Registers All PHY_Sx registers have the same structure and characteristics, see PHY_S0. The offset addresses of the other PHY_Sx registers are ...
Page 191
Field Bits Type PHY_ID 15:0 ro Similar Registers All PHY_Ix_A registers have the same structure and characteristics, see PHY_I0_A. The offset addresses of the other PHY_Ix_A registers are listed in Table 68 PHY_Ix_A Registers Register Short Name Register Long Name ...
Page 192
Table 69 PHY_Ix_B Registers Register Short Name Register Long Name PHY_I1_B PHY Identifier Register of Port 1 (B) PHY_I2_B PHY Identifier Register of Port 2 (B) PHY_I3_B PHY Identifier Register of Port 3 (B) PHY_I4_B PHY Identifier Register of Port ...
Page 193
Field Bits Type TX_HDX 7 rw 10_FDX 6 rw 10_HDX 4:0 ro Similar Registers All ANAPx registers have the same structure and characteristics, see ANAP0. The offset addresses of the other ANAPx registers are listed in Table ...
Page 194
Field Bits Type ACK LP_DIR 11 ro LP_PAU 10 ro LP_T4 9 ro LP_FDX 8 ro LP_HDX 7 ro LP_F10 6 ro LP_H10 4:0 ro Similar Registers All ANLPAx registers have the ...
Page 195
ANE0 Auto Negotiation Expansion Register of Port 0 Field Bits Type PFAULT 4 ro, lh LPNPABLE 3 ro NPABLE 2 ro PGRCV 1 ro LPANABLE 0 ro Similar Registers All ANEx registers have the same structure and characteristics, see ANE0. ...
Page 196
Field Bits Type TNPAGE 15 ro TMSG 13 rw TACK2 12 rw TTOG 11 ro TFLD 10:0 rw Similar Registers All NPTx registers have the same structure and characteristics, see NPT0. The offset addresses of the other NPTx registers are ...
Page 197
Field Bits Type PACK 14 ro PMSGP 13 ro PACK2 12 ro PTOG 11 ro PFLD 10:0 ro Similar Registers All LPNPx registers have the same structure and characteristics, see LPNP0. The offset addresses of the other LPNPx registers are ...
Page 198
Electrical Specification 5.1 TX/FX Interface 5.1.1 TP Interface TXP TXN ADM6996 RXP RXN Figure 17 TP Interface Transformer requirements: • TX/RX rate 1:1 • TX/RX central tap connect together to VCCA2 Users can change the TX/RX pin for easy ...
Page 199
FX Interface TXP TXN ADM6996 RXP RXN Figure 18 FX Interface 5.2 DC Characterization Table 75 Power Consumption Parameter Power consumption when all twisted pair ports are linked at 100 Mbit/s. Power consumption when all twisted pair ports are ...
Page 200
Table 76 Absolute Maximum Ratings Parameter 3.3 V Power Supply for I/O pad 3.3 V Power Supply for bias circuit 3.3 V Power Supply for A/D converter 1.8 V Power Supply for line driver 1.8 V Power Supply for PLL ...