EASY 6996M CPU Infineon Technologies, EASY 6996M CPU Datasheet - Page 81
![BOARD EVAL W/CPU ADM6996M](/photos/9/10/91037/easy_6996m_cpu_sml.jpg)
EASY 6996M CPU
Manufacturer Part Number
EASY 6996M CPU
Description
BOARD EVAL W/CPU ADM6996M
Manufacturer
Infineon Technologies
Series
Samurair
Datasheet
1.EASY_6996M_CPU.pdf
(216 pages)
Specifications of EASY 6996M CPU
Main Purpose
Interface, Ethernet
Embedded
No
Utilized Ic / Part
ADM6996M
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Primary Attributes
-
Other names
EASY6996MCPUIN
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Table 52
Register Short Name
SC4
P0SO
P1SO
P2SO
P3SO
P4SO
P5SO
UFGPM
BFGPM
MFGPM
RFGPM
PIOFGPM
VPEFGPM
SPEFGPM
IFNTFGPM
IFFGPM
VSDFGPM
BT0
BT1
IMEIJT
Q2WVECPO
Q3WBPVAO
IDTEP
ODTEP
OTBP
P11_4
RACP
PHYC
ATET
PR
MISC
BBC0
BBC1
BCE
EBC0
Data Sheet
Registers Overview (cont’d)
Register Long Name
System Control Register 4
Port 0 Security Option
Port 1 Security Option
Port 2 Security Option
Port 3 Security Option
Port 4 Security Option
Port 5 Security Option
Unicast Port Map andForward Group Port Map
Broadcast Port Map andForward Group Port Map 1A
Multicast Port Map and Forward Group Port Map
Reserve Port Map and Forward Group Port Map
Packet Identification Option, Forward Group Port
Map
VLAN Priority Enable and Forward Group Port
Map
Service Priority Enable and Forward Group Port
Map
Input Force No Tag and Forward Group Port Map 20
Ingress Filter andForward Group Port Map
VLAN Security Disable and Forward Group Port
Map
Buffer Threshold Register 0
Buffer Threshold Register 1
IGMP/MLDTRAP Enable and Input Jam Threshold
Register
Queue 2 Weight, VID Exist Check, and PPPOE
Port Only
Queue 3 Weight, Back to Port VLAN, and Admit
Only VLAN-Tagged
Input Double Tag Enable, and P0VID[11:4]
Output Double Tag Enable, and P1VID[11:4]
Output Tag Bypass, and P2VID[11:4]
P3VID[11:4], and P4VID[11:4]
Reserved Address Control, and P5VID[11:4]
PHY Control Register
ADM TAG Ether Type
PHY Restart Register
Miscellaneous Register
Basic Bandwidth Control Register 0
Basic Bandwidth Control Register 1
Bandwidth Control Enable Register
Extended Bandwidth Control Register 0
81
Offset Address
12
13
14
15
16
17
18
19
1B
1C
1D
1E
1F
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Revision 1.4, 2006-03-24
Registers Description
Samurai-6M/MX
ADM6996M/MX
Page Number
104
106
107
107
107
107
107
108
108
109
110
111
112
113
114
115
116
118
118
118
119
119
120
120
121
121
122
122
123
124
124
125
126
127
128
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