EASY 6996M CPU Infineon Technologies, EASY 6996M CPU Datasheet - Page 17

• Manufacturer Part Number: EASY 6996M CPU
• Description: BOARD EVAL W/CPU ADM6996M
• Manufacturer: Infineon Technologies
• Series: Samurair

Specifications of EASY 6996M CPU

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: ADM6996M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Primary Attributes: -
• Other names: EASY6996MCPUIN

Table 3
Ball No.
106
105
103
104
Data Sheet
IO Signals (cont’d)
Name
P4_BUSMD0
MMII_P4TXD0
PMII_P4TXD0
P4_BUSMD1
MMII_P4TXD1
PMII_P4TXD1
MMII_P4TXD3
PMII_P4TXD3
MMII_P4TXD2
PMII_P4TXD2
Pin
Type
I
O
I
I
O
I
O
I
O
I
Buffer
Type
PD,
LVTTL
8 mA,
PD,
LVTTL
PD,
LVTTL
PD,
LVTTL
8 mA,
PD,
LVTTL
PD,
LVTTL
8 mA,
PD,
LVTTL
PD,
LVTTL
8 mA,
PD,
LVTTL
PD,
LVTTL
Function
Port 4 Bus Type Configuration 0
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) at the rising edge of RESETL(RC) for
Port 4 Configuration Bit 0. Combined with
P4_BUSMD1, Samurai-6M/6MX (ADM6996M/MX)
provides 4 bus type for port 4. See
more details.
Note: Power On Setting
Port 4 Transmit Data Bit 0 in MAC MII Mode
The LSB bit of MAC MII Transmit data of port 4.
Synchronous to the rising edge of MMII_P4TXCLK.
Port 4 Transmit Data Bit 0 in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is the
LSB of MII transmit data input and synchronous to the rising
edge of PMII_P4TXCLK.
Port 4 Bus Type Configuration 1
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) at the rising edge of RESETL(RC) for
Port 4 Configuration Bit 1. Combined with
P4_BUSMD0, Samurai-6M/6MX (ADM6996M/MX)
provides 4 bus type for port 4. See
Note: Power On Setting
Port 4 Transmit Data Bit 1 in MAC MII Mode
The bit[1] of MAC MII Transmit data of port 4. Synchronous
to the rising edge of MMII_P4TXCLK.
Port 4 Transmit Data Bit 1 in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is bit[1]
of MII transmit data input and synchronous to the rising
edge of PMII_P4TXCLK.
Port 4 Transmit Data Bit 3 in MAC MII Mode
The bit[3] of MAC MII Transmit data of port 4. Synchronous
to the rising edge of MMII_P4TXCLK.
Port 4 Transmit Data Bit 3 in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is bit[3]
of MII transmit data input and synchronous to the rising
edge of PMII_P4TXCLK.
Port 4 Transmit Data Bit 2 in MAC MII Mode
The bit[2] of MAC MII Transmit data of port 4. Synchronous
to the rising edge of MMII_P4TXCLK.
Port 4 Transmit Data Bit 2 in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is bit[2]
of MII transmit data input and synchronous to the rising
edge of PMII_P4TXCLK.
17
CFG0
Revision 1.4, 2006-03-24
CFG0
Interface Description
Samurai-6M/MX
ADM6996M/MX
pin description for
for more details.
CFG0
CFG0
and
and