EASY 6996M CPU Infineon Technologies, EASY 6996M CPU Datasheet - Page 89

• Manufacturer Part Number: EASY 6996M CPU
• Description: BOARD EVAL W/CPU ADM6996M
• Manufacturer: Infineon Technologies
• Series: Samurair

Specifications of EASY 6996M CPU

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: ADM6996M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Primary Attributes: -
• Other names: EASY6996MCPUIN

Table 53
Mode
read/write
read
Read only
Read virtual
Latch high,
self clearing
Latch low,
self clearing
Latch high,
mask clearing
Latch low,
mask clearing
Interrupt high,
self clearing
Interrupt low,
self clearing
Interrupt high,
mask clearing
Interrupt low,
mask clearing
Interrupt enable
register
latch_on_reset
Read/write
self clearing
Table 54
Clock Short Name
–
Data Sheet
Register Access Types
Registers Clock Domains
Symbol Description HW
rw
r
ro
rv
lhsc
llsc
lhmk
llmk
ihsc
ilsc
ihmk
ilmk
ien
lor
rwsc
Register is used as input for the HW
Physically, there is no new register, the
Register is written by HW (register
between input and output -> one cycle
delay)
Register is set by HW (register between
input and output -> one cycle delay)
input of the signal is connected directly
to the address multiplexer.
Latches high signal at high level,
cleared on read
Latches high signal at low-level,
cleared on read
Latches high signal at high level,
register cleared with written mask
Latches high signal at low-level,
register cleared on read
Differentiates the input signal (low-
>high) register cleared on read
Differentiates the input signal (high-
>low) register cleared on read
Differentiates the input signal (high-
>low) register cleared with written mask
Differentiates the input signal (low-
>high) register cleared with written
mask
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
Register is used as input for the hw, the
register will be cleared due to a HW
mechanism.
Description
–
89
Description SW
Register is readable and writable by SW
Value written by software is ignored by
hardware; that is, software may write any
value to this field without affecting hardware
behavior (= Target for development.)
SW can only read this register
SW can only read this register
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared
SW can read the register, with write mask
the register can be cleared
SW can read and write this register
Register is readable and writable by SW
Writing to the register generates a strobe
signal for the HW (1 pdi clock cycle)
Register is readable and writable by SW.
Revision 1.4, 2006-03-24
Registers Description
Samurai-6M/MX
ADM6996M/MX