EASY 6996M CPU Infineon Technologies, EASY 6996M CPU Datasheet - Page 20

• Manufacturer Part Number: EASY 6996M CPU
• Description: BOARD EVAL W/CPU ADM6996M
• Manufacturer: Infineon Technologies
• Series: Samurair

Specifications of EASY 6996M CPU

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: ADM6996M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Primary Attributes: -
• Other names: EASY6996MCPUIN

Table 3
Ball No.
60
59
66
53
Data Sheet
IO Signals (cont’d)
Name
P5_BUSMD1
MII_P5TXD2
SDIO_MD
MII_P5TXD3
PHYAS0
MII_P5TXEN
GPSI_P5TXEN
RMII_P5TXEN
MII_P5RXD0
GPSI_P5RXD
RMII_P5RXD0
Pin
Type
I
O
I
O
I
O
O
O
I
I
I
Buffer
Type
PD,
LVTTL
4 mA,
PD,
LVTTL
PD,
LVTTL
4 mA,
PD,
LVTTL
PD,
LVTTL
8 mA,
PD,
LVTTL
8 mA,
PD,
LVTTL
8 mA,
PD,
LVTTL
PD,
LVTTL
PD,
LVTTL
PD,
LVTTL
Function
Port 5 Bus Mode Selection Bit 1
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) at the rising edge of RESETL(RC) as port
5 bus mode selection bit 1. See
details.
Note: Power On Setting
Port 5 Transmit Data Bit 2 in MII Mode
The bit[2] of MII Transmit data of port 5. Synchronous to the
rising edge of MII_P5TXCLK.
SDC/SDIO Mode Selection
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) at the rising edge of RESETL(RC) as
SDC/SDIO
mode.
Note: Power On Setting
0
Port 5 Transmit Data Bit 3 in MII Mode
The MSB bit of MII Transmit data of port 5. Synchronous to
the rising edge of MII_P5TXCLK.
PHY Address MSB Bit 0
During power on reset, value will be latched by Samurai-
6M/6MX (ADM6996M/MX) at the rising edge of
RESETL(RC) as PHY start address select.
PHYAS[1:0] = 00
Note: Power On Setting
Port 5 Transmit Enable TXEN in MII Mode
Active high to indicate that the data on MII_P5TXD[3:0] is
valid. Synchronous to the rising edge of MII_P5TXCLK.
Port 5 Transmit Enable TXEN in GPSI Mode
Active high to indicate that the data on GPSI_P5TXD is
valid. Synchronous to the rising edge of GPSI_P5TXCLK.
Port 5 Transmit Enable TXEN in RMII Mode
Active high to indicate that the data on RMII_P5TXD[1:0] is
valid. Synchronous to the rising edge of REFCLK_IN.
Port 5 Receive Data Bit 0 in MII Mode
In MII mode, the bit is the LSB of MII receive data,
synchronous to the rising edge of MII_P5RXCLK.
Port 5 Receive Data in GPSI Mode
In GPSI Mode, this acts as Receive Data Input,
synchronous to the rising edge of GPSI_P5RXCLK.
Port 5 Receive Data Bit 0 in RMII Mode
In RMII mode, the bit is the LSB of RMII receive data,
synchronous to the rising edge of REFCLK_IN.
B
20
16 bits mode, MDC/MDIO timing compatible
control signal which is used to select 16 bit
B
and PHY address starts from 01000
P5_BUSMD0
Revision 1.4, 2006-03-24
Interface Description
Samurai-6M/MX
ADM6996M/MX
for more
B
.