OM11014 NXP Semiconductors, OM11014 Datasheet
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LPC2917/19 ARM9 microcontroller with CAN and LIN Rev. 01 — 31 July 2008 1. Introduction 1.1 About this document This document lists detailed information about the LPC2917/19 device. It focuses on factual information like pinning, characteristics etc. Short descriptions are ...
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... NXP Semiconductors 2.2 ARM968E-S processor The ARM968E general purpose 32-bit RISC processor, which offers high performance and very low power consumption. The ARM architecture is based on RISC principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed CISC. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective controller core ...
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... NXP Semiconductors 2.4 On-chip static RAM In addition to the two 16 kB TCMs the LPC2917/19 includes two static RAM memories: one and one of 16 kB. Both may be used for code and/or data storage. 3. Features 3.1 General I ARM968E-S processor at 80 MHz maximum. I AHB system bus at 80 MHz. ...
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... NXP Semiconductors N Allows minimization of system operating power consumption in any configuration. I Standard ARM test and debug interface with real-time in-circuit emulator. I Boundary-scan test supported. I Dual power supply: N CPU operating voltage: 1 I/O operating voltage: 2 3.6 V; inputs tolerant 144-pin LQFP package ambient operating temperature range. ...
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... NXP Semiconductors 5. Block diagram LPC2917/2919 VECTORED INTERRUPT CONTROLLER CLOCK GENERATION UNIT RESET GENERATION UNIT POWER MANAGEMENT UNIT TIMER0/1 MTMR PWM0/1/2/3 ADC1/2 CAN0/1 GLOBAL ACCEPTANCE FILTER LIN0/1 Fig 1. LPC2917/19 block diagram LPC2917_19_1 Product data sheet JTAG interface TEST/DEBUG INTERFACE ITCM DTCM 16 kB ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description 6.2.1 General description The LPC2917/19 has up to four ports: two of 32 pins each, one of 28 pins and one of 16 pins. The pin to which each function is assigned is controlled by the SFSP registers in the SCU ...
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... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name P2[24]/PCAP3[1]/D22 P2[25]/PCAP3[2]/D23 V DD(CORE) V SS(CORE) P1[31]/CAP0[1]/MAT0[1]/EI5 V SS(IO) P1[30]/CAP0[0]/MAT0[0]/EI4 P3[8]/SCS2[0]/PMAT1[2] P3[9]/SDO2/PMAT1[3] P1[29]/CAP1[0]/TRAP0/ PMAT3[5] P1[28]/CAP1[1]/TRAP1/ PMAT3[4] P2[26]/CAP0[2]/MAT0[2]/EI6 ...
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... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name P1[13]/EI3/WE_N P1[12]/EI2/OE_N V DD(IO) P2[2]/MAT2[2]/TRAP1/D10 P2[3]/MAT2[3]/TRAP0/D11 P1[11]/SCK1/CS3 P1[10]/SDI1/CS2 P3[12]/SCS1[0]/EI4 V SS(CORE) V DD(CORE) P3[13]/SDO1/EI5 P2[4]/MAT1[0]/EI0/D12 P2[5]/MAT1[1]/EI1/D13 P1[9]/SDO1/RXDL1/CS1 V SS(IO) P1[8]/SCS1[0]/TXDL1/CS0 ...
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... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name P2[10]/PMAT0[2]/SCS0[0] P2[11]/PMAT0[3]/SCK0 P0[0]/TXDC0/D24 V SS(IO) P0[1]/RXDC0/D25 P0[2]/PMAT0[0]/D26 P0[3]/PMAT0[1]/D27 P3[0]/PMAT2[0]/CS6 P3[1]/PMAT2[1]/CS7 P2[12]/PMAT0[4]/SDI0 P2[13]/PMAT0[5]/SDO0 P0[4]/PMAT0[2]/D28 P0[5]/PMAT0[3]/D29 ...
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... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name P2[17]/RXD1/PCAP1[0]/BLS3 V DD(IO) P0[18]/IN2[2]/PMAT2[0]/A14 P0[19]/IN2[3]/PMAT2[1]/A15 P3[4]/MAT3[2]/PMAT2[4]/TXDC1 P3[5]/MAT3[3]/PMAT2[5]/RXDC1 P2[18]/PCAP1[1]/D16 P2[19]/PCAP1[2]/D17 P0[20]/IN2[4]/PMAT2[2]/A16 P0[21]/IN2[5]/PMAT2[3]/A17 ...
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... NXP Semiconductors 7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test) The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also referred to in this document as JTAG. The boundary-scan test pins can be used to connect a debugger probe for the embedded ARM processor. Pin JTAGSEL selects between boundary-scan mode and debug mode ...
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... NXP Semiconductors LPC2917/2919 VECTORED INTERRUPT SYS_CLK CONTROLLER RESET/CLOCK GENERATION PCR_CLK POWER MANAGEMENT MSCSS_CLK TIMER0/1 MTMR PWM0/1/2/3 ADC_CLK ADC1/2 IVNSS_CLK Fig 3. LPC2917/19 block diagram, overview of clock areas 7.2.2 Base clock and branch clock relationship The next table contains an overview of all the base blocks in the LPC2917/19 and their derived branch clocks ...
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... NXP Semiconductors found in the specific subsystem description. Some branch clocks have special protection since they clock vital system parts of the device and should (for example) not be switched off. See Table 7. Base clock BASE_SAFE_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK BASE_MSCSS_CLK LPC2917_19_1 Product data sheet Section 8 ...
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... NXP Semiconductors Table 7. Base clock BASE_UART_CLK BASE_SPI_CLK BASE_TMR_CLK BASE_ADC_CLK BASE_CLK_TESTSHELL [1] This clock is always on (cannot be switched off for system safety reasons) [2] In the peripheral subsystem parts of the Timers, watchdog timer, SPI and UART have their own clock source. See [3] In the Power Clock and Reset Control subsystem parts of the CGU, RGU PMU have their own clock source. ...
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... NXP Semiconductors 8.1.2 Description After reset flash initialization is started, which takes t initialization flash access is not possible and AHB transfers to flash are stalled, blocking the AHB bus. During flash initialization the index sector is read to identify the status of the JTAG access protection and sector security. If JTAG access protection is active the flash is not accessible via JTAG. ARM debug facilities are disabled to protect the fl ...
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... NXP Semiconductors Table 8. Synchronous timing No buffer line Single buffer line Asynchronous timing No buffer line Single buffer line Dual buffer line, single speculative Dual buffer line, always speculative 8.1.3 Flash memory controller pin description The flash memory controller has no external pins. However, the flash can be programmed via the JTAG pins, see 8 ...
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... NXP Semiconductors Table 9. Sector number [1] 15 [1] 16 [1] 17 [1] 18 [1] Availability of sector 15 to sector 18 depends on device type, see The index sector is a special sector in which the JTAG access protection and sector security are located. The address space becomes visible by setting the FS_ISS bit and overlaps the regular fl ...
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... NXP Semiconductors • Asynchronous page-mode read operation in non-clocked memory subsystems • Asynchronous burst-mode read access to burst-mode ROM devices • Independent configuration for up to eight banks, each • Programmable bus-turnaround (idle) cycles (one to 16) • Programmable read and write wait states (up to 32), for static RAM devices • ...
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... NXP Semiconductors 8.2.3 External static-memory controller pin description The external static-memory controller module in the LPC2917/19 has the following pins, which are combined with other functions on the port pins of the LPC2917/19. shows the external memory controller pins. Table 12. Symbol EXTBUS CSx EXTBUS BLSy ...
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... NXP Semiconductors Fig 5. Usage of the idle/turn-around time (IDCY) is demonstrated In are added between a read and a write cycle in the same external memory device. CLK(SYS) WE_N/BLS OE_N ADDR DATA Fig 6. LPC2917_19_1 Product data sheet CLK(SYS) CS WE_N/BLS ADDR DATA WSTWEN WSTWEN = 3, WST2 = 7 Writing to external memory ...
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... NXP Semiconductors Address pins on the device are shared with other functions. When connecting external memories, check that the I/O pin is programmed for the correct function. Control of these settings is handled by the SCU. 8.3 General subsystem 8.3.1 General subsystem clock description The general subsystem is clocked by CLK_SYS_GESS, see 8.3.2 Chip and feature identifi ...
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... NXP Semiconductors • Latched events remain active until they are explicitly cleared • Programmable input level and edge polarity • Event detection maskable • Event detection is fully asynchronous clock is required 8.3.4.2 Description The event router allows the event source to be defined, its polarity and activation type to be selected and the interrupt to be masked or enabled ...
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... NXP Semiconductors • CLK_UART0/1 • CLK_SPI0/1/2 • CLK_TMR0/1/2/3 • CLK_SAFE see 8.4.2 Watchdog timer 8.4.2.1 Overview The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable amount of time if the processor enters an error state. The watchdog generates a system reset if the user program fails to trigger it correctly within a predetermined amount of time. ...
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... NXP Semiconductors 8.4.3 Timer 8.4.3.1 Overview The LPC2917/19 contains six identical timers: four in the peripheral subsystem and two in the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral base addresses. This section describes the four timers in the peripheral subsystem. Each timer has four capture inputs and/or match outputs. Connection to device pins depends on the confi ...
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... NXP Semiconductors timers and their associated pins. The timer pins are combined with other functions on the port pins of the LPC2917/19, see runs from 0 to 3). Table 14. Symbol TIMERx CAP[0] TIMERx CAP[1] TIMERx CAP[2] TIMERx CAP[3] TIMERx MAT[0] TIMERx MAT[1] TIMERx MAT[2] TIMERx MAT[3] 8.4.3.4 Timer clock description The timer modules are clocked by two different clocks ...
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... NXP Semiconductors 8.4.4.4 UART clock description The UART modules are clocked by two different clocks; CLK_SYS_PESS and CLK_UARTx (x = 0-1), see branch clock for power management. The frequency of all CLK_UARTx clocks is identical since they are derived from the same base clock BASE_CLK_UART. The register interface towards the system bus is clocked by CLK_SYS_PESS ...
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... NXP Semiconductors Depending on the operating mode selected, the SPI_CS_OUT outputs operate as an active-HIGH frame synchronization output for Texas Instruments synchronous serial frame format or an active-LOW chip select for SPI. Each data frame is between four and 16 bits long, depending on the size of words programmed, and is transmitted starting with the MSB ...
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... NXP Semiconductors 8.4.6 General-purpose I/O 8.4.6.1 Overview The LPC2917/19 contains four general-purpose I/O ports located at different peripheral base addresses. In the 144-pin package all four ports are available. All I/O pins are bidirectional, and the direction can be programmed individually. The I/O pad behavior depends on the confi ...
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... NXP Semiconductors 8.5 CAN gateway 8.5.1 Overview Controller Area Network (CAN) is the definition of a high-performance communication protocol for serial data communication. The two CAN controllers in the LPC2917/19 provide a full implementation of the CAN protocol according to the CAN specification version 2.0B . The gateway concept is fully scalable with the number of CAN controllers, and always operates together with a separate powerful and fl ...
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... NXP Semiconductors • Complete LIN 2.0 message handling and transfer • One interrupt per LIN message • Slave response time-out detection • Programmable sync-break length • Automatic sync-field and sync-break generation • Programmable inter-byte space • Hardware or software parity generation • ...
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... NXP Semiconductors control. Several other trigger possibilities are provided for the ADCs (external, cascaded or following a PWM). The capture inputs of both timers can also be used to capture the start pulse of the ADCs. The PWMs can be used to generate waveforms in which the frequency, duty cycle and rising and falling edges can be controlled very precisely ...
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... NXP Semiconductors Each ADC module has four start inputs. An ADC conversion is started when one of the start ADC conditions is valid: • Start 0: ADC external start input pin; can be triggered at a positive or negative edge. Note that this signal is captured in the ADC clock domain • ...
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... NXP Semiconductors ADC2_EXT_START ADC1_EXT_START pause_0 pause (1) MSCSS TIMER 0 so0 so1 so2 c2 m2 pause_0 c3 m3 MSCSS PAUSE PWM0 TRAP PWM1 TRAP PWM2 TRAP PWM3 TRAP (1) Timers capture capture match out 0 to match out 3 (2) ADCs: st0 to st3 = start 0 to start 3 inputs sync_out 0 to sync_out 3 ...
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... NXP Semiconductors • CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-APB bus bridge • CLK_MSCSS_APB clocks the subsystem APB bus • CLK_MSCSS_MTMR0/1 clocks the timers • CLK_MSCSS_PWM0..3 clocks the PWMs. Each ADC has two clock areas; a APB part clocked by CLK_MSCSS_ADCx_APB ( and a control part for the analog section clocked by CLK_ADCx = 1 or 2), see ...
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... NXP Semiconductors system-clock divider dedicated to the ADC clock. Conversion rate is determined by the ADC clock frequency divided by the number of resolution bits plus one. Accessing ADC registers requires an enabled ADC clock, which is controllable via the clock generation unit, see Each ADC has four start inputs. Note that start 0 and start 2 are captured in the system clock domain while start 1 and start 3 are captured in the ADC domain ...
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... NXP Semiconductors The frequency of all the CLK_MSCSS_ADCx_APB clocks is identical to CLK_MSCSS_APB since they are derived from the same base clock BASE_MSCSS_CLK. Likewise the frequency of all the CLK_ADCx clocks is identical since they are derived from the same base clock BASE_ADC_CLK. The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_APB. ...
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... NXP Semiconductors APB system bus IRQ pwm IRQ capt_match Fig 10. PWM block diagram The PWM block diagram in functionality is split into two major parts, a APB domain and a PWM domain, both of which run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects behavior from a system-level perspective ...
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... NXP Semiconductors 8.7.6.4 Master and slave mode A PWM module can provide synchronization signals to other modules (also called Master mode). The signal sync_out is a pulse of one clock cycle generated when the internal PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync_out, generated if a transfer from system registers to PWM shadow registers occurred when the PWM counter restarted ...
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... NXP Semiconductors 8.7.7.2 Description See section 8.7.7.3 MSCSS timer-pin description MSCSS timer 0 has no external pins. MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined with other functions on the port pins of the LPC2917/19. timer 1 external pin. Table 22. Symbol MSCSS PAUSE 8 ...
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... NXP Semiconductors EXTERNAL OSCILLATOR LOW POWER RING OSCILLATOR CGU REGISTERS AHB2DTL BRIDGE RGU REGISTERS POR Fig 11. PCRSS block diagram LPC2917_19_1 Product data sheet CGU PLL OUT0 OUT1 0UT9 FDIV[6:0] RGU RESET OUTPUT DELAY LOGIC INPUT DEGLITCH/ SYNC RST_N (device pin) reset from watchdog counter Rev. 01 — ...
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... NXP Semiconductors 8.8.3 PCR subsystem clock description The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and PMU internal logic, see BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is derived from BASE_PCR_CLK and is always on in order to be able to wake up from low-power modes ...
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... NXP Semiconductors For generation of these base clocks, the CGU consists of primary and secondary clock generators and one output generator for each base clock. CLOCK GENERATION UNIT (CGU) LP_OSC EXTERNAL OSCLLLATOR FREQUENCY MONITOR Fig 12. Block diagram of the CGU There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a crystal oscillator ...
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... NXP Semiconductors Fig 13. Structure of the clock generation scheme Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be connected to either a fractional divider (FDIV0.. one of the outputs of the PLL or to LP_OSC/crystal oscillator directly. BASE_SAFE_CLK and BASE_PCR_CLK can use only LP_OSC as source. The fractional dividers can be connected to one of the outputs of the PLL or directly to LP_OSC/crystal Oscillator ...
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... NXP Semiconductors appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock detector can also generate interrupts at clock activation and deactivation so that the system can be notifi change in internal clock status. Clock detection is done using a counter running at the BASE_PCR_CLK frequency positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock is assumed to be inactive ...
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... NXP Semiconductors Triple output phases: clock outputs can be enabled by setting register P23EN to logic 1, thus giving three clocks with a 120 phase difference. In this mode all three clocks generated by the analog section are sent to the output dividers. When the PLL has not yet achieved lock the second and third phase output dividers run unsynchronized, which means that the phase relation of the output clocks is unknown ...
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... NXP Semiconductors Table 25. Reset output POR_RST RGU_RST PCR_RST COLD_RST WARM_RST SCU_RST CFID_RST FMC_RST EMC_RST SMC_RST GESS_A2V_RST PESS_A2V_RST GPIO_RST UART_RST TMR_RST SPI_RST IVNSS_A2V_RST IVNSS_CAN_RST IVNSS_LIN_RST MSCSS_A2V_RST MSCSS_PWM_RST MSCSS_ADC_RST MSCSS_TMR_RST VIC_RST AHB_RST 8.8.5.3 RGU pin description The RGU module in the LPC2917/19 has the following pins. ...
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... NXP Semiconductors The key features are: • Individual clock control for all LPC2917/19 sub-modules • Activates sleeping clocks when a wake-up event is detected • Clocks can be individually disabled by software • Supports AHB master-disable protocol when AUTO mode is set • Disables wake-up of enabled clocks when Power-down mode is set • ...
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... NXP Semiconductors Table 27. Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’ Indicates that the related register bit is readable and writable ...
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... NXP Semiconductors Table 27. Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’ Indicates that the related register bit is readable and writable ...
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... NXP Semiconductors • Priority 15 corresponds to the highest priority Software interrupt support is provided and can be supplied for: • Testing Real-Time Operating System (RTOS) interrupt handling without using device-specific interrupt service routines • Software emulation of an interrupt-requesting device, including interrupts 8.9.3 VIC pin description The VIC module in the LPC2917/19 has no external pins ...
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... NXP Semiconductors 9. Limiting values Table 28. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Supply pins P total power dissipation tot V core supply voltage DD(CORE) V oscillator and PLL supply DD(OSC_PLL) voltage V 3.3 V ADC analog supply DDA(ADC3V3) voltage V I/O supply voltage ...
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... NXP Semiconductors Table 28. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter ESD V electrostatic discharge esd voltage [1] Based on package heat transfer, not device power consumption. [2] Peak current must be limited at 25 times average current. [3] For I/O Port 0, the maximum input voltage is defined by V ...
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... NXP Semiconductors 11. Static characteristics Table 30. Static characteristics DD(CORE) DD(OSC_PLL) DD(IO) measured with respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter Supplies Core supply V core supply voltage DD(CORE) I core supply current DD(CORE) I/O supply V I/O supply voltage ...
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... NXP Semiconductors Table 30. Static characteristics DD(CORE) DD(OSC_PLL) DD(IO) measured with respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter I LOW-level input leakage LIL current I pull-down input current I(pd) I pull-up input current I(pu) C input capacitance i Output pins and I/O pins configured as output ...
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... NXP Semiconductors Table 30. Static characteristics DD(CORE) DD(OSC_PLL) DD(IO) measured with respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter Power-up reset V high trip level voltage trip(high) V low trip level voltage trip(low) V difference between high trip(dif) and low trip level voltage [1] All parameters are guaranteed over the virtual junction temperature range by design ...
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... NXP Semiconductors 12. Dynamic characteristics Table 31. Dynamic characteristics DD(CORE) DD(OSC_PLL) DD(IO) respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter I/O pins t HIGH-to-LOW THL transition time t LOW-to-HIGH TLH transition time Internal clock f system clock frequency clk(sys) T system clock period ...
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... NXP Semiconductors Table 31. Dynamic characteristics DD(CORE) DD(OSC_PLL) DD(IO) respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter External static memory controller t internal read access a(R)int time t internal write access a(W)int time UART f UART frequency UART SPI f SPI operating ...
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... NXP Semiconductors 13. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . LPC2917_19_1 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature ...
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... NXP Semiconductors 15. Abbreviations Table 34. Abbreviation ADC AHB AMBA APB BCL BDL BEL BIST CAN CCO CISC DAC DTL FIFO FIQ GPIO I/O IAP IRQ ISP JTAG LIN MAC PLL PCRSS PWM RISC RTOS RX SFSP SCL SCU SPI SSP TAP TCM TX UART ...
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... NXP Semiconductors 16. References [1] UM — LPC2917/19 user manual [2] ARM — ARM web site [3] ARM-SSP — ARM primecell synchronous serial port (PL022) technical reference manual [4] CAN — ISO 11898-1: 2002 road vehicles - Controller Area Network (CAN) - part 1: data link layer and physical signalling [5] LIN — ...
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... NXP Semiconductors 17. Revision history Table 35. Revision history Document ID Release date LPC2917_19_1 20080731 LPC2917_19_1 Product data sheet ARM9 microcontroller with CAN and LIN Data sheet status Change notice Product data sheet - Rev. 01 — 31 July 2008 LPC2917/19 Supersedes - © NXP B.V. 2008. All rights reserved. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 20. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 About this document . . . . . . . . . . . . . . . . . . . . . 1 1.2 Intended audience . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Architectural overview 2.2 ARM968E-S processor . . . . . . . . . . . . . . . . . . . 2 2.3 On-chip flash memory system . . . . . . . . . . . . . 2 2.4 On-chip static RAM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information ...
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... NXP Semiconductors 8.7 Modulation and sampling control subsystem . 30 8.7.1 Overview 8.7.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.7.2.1 Synchronization and trigger features of the MSCSS . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.7.3 MSCSS pin description 8.7.4 MSCSS clock description . . . . . . . . . . . . . . . . 33 8.7.5 Analog-to-digital converter . . . . . . . . . . . . . . . 34 8.7.5.1 Overview 8.7.5.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.7.5.3 ADC pin description . . . . . . . . . . . . . . . . . . . . 35 8.7.5.4 ADC clock description ...