OM11014 NXP Semiconductors, OM11014 Datasheet - Page 14

• Manufacturer Part Number: OM11014
• Description: BOARD EVAL FOR LPC2919
• Manufacturer: NXP Semiconductors
• Series: Keilr
• Type: MCUr

Specifications of OM11014

• Contents: Board, Cable, CD
• For Use With/related Products: LPC2919
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Other names: 568-4360

NXP Semiconductors
8. Block description
LPC2917_19_1
Product data sheet
8.1.1 Overview
8.1 Flash memory controller
Table 7.
[1]
[2]
[3]
[4]
The Flash Memory Controller (FMC) interfaces to the embedded flash memory for two
tasks:
The flash memory has a 128-bit wide data interface and the flash controller offers two
128-bit buffer lines to improve system performance. The flash has to be programmed
initially via JTAG. In-system programming must be supported by the bootloader.
In-application programming is possible. Flash memory contents can be protected by
disabling JTAG access. Suspension of burning or erasing is not supported.
The key features are:
Base clock
BASE_UART_CLK
BASE_SPI_CLK
BASE_TMR_CLK
BASE_ADC_CLK
BASE_CLK_TESTSHELL
•
•
•
•
•
•
This clock is always on (cannot be switched off for system safety reasons)
In the peripheral subsystem parts of the Timers, watchdog timer, SPI and UART have their own clock
source. See
In the Power Clock and Reset Control subsystem parts of the CGU, RGU PMU have their own clock source.
See
The clock should remain activated when system wake-up on timer or UART is required.
Providing memory data transfer
Memory configuration via triggering, programming and erasing
Programming by CPU via AHB
Programming by external programmer via JTAG
JTAG access protection
Burn-finished and erase-finished interrupt
Section 8.8
Base clock and branch clock overview
Section 8.4
for details.
Rev. 01 — 31 July 2008
for details.
Branch clock name
CLK_UART0
CLK_UART1
CLK_SPI0
CLK_SPI1
CLK_SPI2
CLK_TMR0
CLK_TMR1
CLK_TMR2
CLK_TMR3
CLK_ADC1
CLK_ADC2
CLK_TESTSHELL_IP
ARM9 microcontroller with CAN and LIN
…continued
Parts of the device clocked by
this branch clock
UART 0 interface clock
UART 1 interface clock
SPI 0 interface clock
SPI 1 interface clock
SPI 2 interface clock
Timer 0 clock for counter part
Timer 1 clock for counter part
Timer 2 clock for counter part
Timer 3 clock for counter part
Control of ADC 1, capture sample
result
Control of ADC 2, capture sample
result
LPC2917/19
© NXP B.V. 2008. All rights reserved.
Remark
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