OM11014 NXP Semiconductors, OM11014 Datasheet - Page 34

• Manufacturer Part Number: OM11014
• Description: BOARD EVAL FOR LPC2919
• Manufacturer: NXP Semiconductors
• Series: Keilr
• Type: MCUr

Specifications of OM11014

• Contents: Board, Cable, CD
• For Use With/related Products: LPC2919
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Other names: 568-4360

NXP Semiconductors
LPC2917_19_1
Product data sheet
8.7.5.1 Overview
8.7.5.2 Description
8.7.5 Analog-to-digital converter
Each ADC has two clock areas; a APB part clocked by CLK_MSCSS_ADCx_APB (x = 1
or 2) and a control part for the analog section clocked by CLK_ADCx = 1 or 2), see
Section
All clocks are derived from the BASE_MSCSS_CLK, except for CLK_SYS_MSCSS_A
which is derived form BASE_SYS_CLK, and the CLK_ADCx clocks which are derived
from BASE_CLK_ADC. If specific PWM or ADC modules are not used their corresponding
clocks can be switched off.
The MSCSS in the LPC2917/19 includes two 10-bit successive-approximation
analog-to-digital converters.
The key features of the ADC interface module are:
The ADC block diagram,
functionality is divided into two major parts; one part running on the MSCSS Subsystem
clock, the other on the ADC clock. This split into two clock domains affects the behavior
from a system-level perspective. The actual analog-to-digital conversions take place in the
ADC clock domain, but system control takes place in the system clock domain.
A mechanism is provided to modify configuration of the ADC and control the moment at
which the updated configuration is transferred to the ADC domain.
The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower than
or equal to the system clock frequency. To meet this constraint or to select the desired
lower sampling frequency the clock generation unit provides a programmable fractional
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CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-APB bus bridge
CLK_MSCSS_APB clocks the subsystem APB bus
CLK_MSCSS_MTMR0/1 clocks the timers
CLK_MSCSS_PWM0..3 clocks the PWMs.
ADC1 and ADC2: Eight analog inputs; time-multiplexed; measurement range up to
3.3 V
External reference-level inputs
400 ksample/s at 10-bit resolution up to 1500 ksample/s at 2-bit resolution
Programmable resolution from 2-bit to 10-bit
Single analog-to-digital conversion scan mode and continuous analog-to-digital
conversion scan mode
Optional conversion on transition on external start input, timer capture/match signal,
PWM_sync or ‘previous’ ADC
Converted digital values are stored in a register for each channel
Optional compare condition to generate a ‘less than’ or an ‘equal to or greater than’
compare-value indication for each channel
Power-down mode
7.2.2.
Rev. 01 — 31 July 2008
Figure
9, shows the basic architecture of each ADC. The ADC
ARM9 microcontroller with CAN and LIN
LPC2917/19
© NXP B.V. 2008. All rights reserved.
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