OM11014 NXP Semiconductors, OM11014 Datasheet - Page 11

• Manufacturer Part Number: OM11014
• Description: BOARD EVAL FOR LPC2919
• Manufacturer: NXP Semiconductors
• Series: Keilr
• Type: MCUr

Specifications of OM11014

• Contents: Board, Cable, CD
• For Use With/related Products: LPC2919
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Other names: 568-4360

NXP Semiconductors
LPC2917_19_1
Product data sheet
7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)
7.1.4 Power supply pins description
7.2.1 Clock architecture
7.2 Clocking strategy
The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also
referred to in this document as JTAG. The boundary-scan test pins can be used to
connect a debugger probe for the embedded ARM processor. Pin JTAGSEL selects
between boundary-scan mode and debug mode.
pins.
Table 5.
Table 6
Table 6.
The LPC2917/19 contains several different internal clock areas. Peripherals like Timers,
SPI, UART, CAN and LIN have their own individual clock sources called Base Clocks. All
base clocks are generated by the Clock Generation Unit (CGU). They may be unrelated in
frequency and phase and can have different clock sources within the CGU.
The system clock for the CPU and AHB Bus infrastructure has its own base clock. This
means most peripherals are clocked independently from the system clock. See
for an overview of the clock areas within the device.
Within each clock area there may be multiple branch clocks, which offers very flexible
control for power-management purposes. All branch clocks are outputs of the Power
Management Unit (PMU) and can be controlled independently. Branch clocks derived
from the same base clock are synchronous in frequency and phase. See
more details of clock and power control within the device.
Symbol
JTAGSEL
TRST_N
TMS
TDI
TDO
TCK
Symbol
V
V
V
V
V
V
V
V
DD(CORE)
SS(CORE)
DD(IO)
SS(IO)
DD(OSC)
SS(OSC)
DDA(ADC3V3)
SS(PLL)
shows the power supply pins.
IEEE 1149.1 boundary-scan test and debug interface
Power supplies
Description
TAP controller select input. LOW-level selects ARM debug mode and HIGH-level
selects boundary scan and flash programming; pulled up internally
test reset input; pulled up internally (active LOW)
test mode select input; pulled up internally
test data input, pulled up internally
test data output
test clock input
Description
digital core supply 1.8 V
digital core ground (digital core, ADC1/2)
I/O pins supply 3.3 V
I/O pins ground
oscillator and PLL supply
oscillator ground
ADC1/2 3.3 V supply
PLL ground
Rev. 01 — 31 July 2008
ARM9 microcontroller with CAN and LIN
Table 5
shows the boundary- scan test
LPC2917/19
© NXP B.V. 2008. All rights reserved.
Section 8.8
Figure 3
11 of 67
for