OM11014 NXP Semiconductors, OM11014 Datasheet - Page 49

• Manufacturer Part Number: OM11014
• Description: BOARD EVAL FOR LPC2919
• Manufacturer: NXP Semiconductors
• Series: Keilr
• Type: MCUr

Specifications of OM11014

• Contents: Board, Cable, CD
• For Use With/related Products: LPC2919
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Other names: 568-4360

NXP Semiconductors
LPC2917_19_1
Product data sheet
8.8.6.3 PMU pin description
8.9.1 Overview
8.9.2 Description
8.9 Vectored interrupt controller
Table 27.
Legend:
‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored
‘+’ Indicates that the related register bit is readable and writable
The PMU has no external pins.
The LPC2917/19 contains a very flexible and powerful Vectored Interrupt Controller (VIC)
to interrupt the ARM processor on request.
The key features are:
The Vectored Interrupt Controller routes incoming interrupt requests to the ARM
processor. The interrupt target is configured for each interrupt request input of the VIC.
The targets are defined as follows:
Interrupt-request masking is performed individually per interrupt target by comparing the
priority level assigned to a specific interrupt request with a target-specific priority
threshold. The priority levels are defined as follows:
Branch clock name
CLK_ADC1
CLK_ADC2
CLK_TESTSHELL_IP
•
•
•
•
•
•
•
•
•
•
•
•
Level-active interrupt request with programmable polarity
56 interrupt-request inputs
Software-interrupt request capability associated with each request input
Observability of interrupt-request state before masking
Software-programmable priority assignments to interrupt requests up to 15 levels
Software-programmable routing of interrupt requests towards the ARM-processor
inputs IRQ and FIQ
Fast identification of interrupt requests through vector
Support for nesting of interrupt service routines
Target 0 is ARM processor FIQ (fast interrupt service)
Target 1 is ARM processor IRQ (standard interrupt service)
Priority level 0 corresponds to ‘masked’ (i.e., interrupt requests with priority 0 never
lead to an interrupt)
Priority 1 corresponds to the lowest priority
Branch clock overview
Rev. 01 — 31 July 2008
Base clock
BASE_ADC_CLK
BASE_ADC_CLK
BASE_CLK_TESTSHELL
…continued
ARM9 microcontroller with CAN and LIN
Implemented switch on/off
mechanism
WAKE-UP
+
+
0
LPC2917/19
AUTO
+
+
0
© NXP B.V. 2008. All rights reserved.
RUN
+
+
1
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