C8051F300DK Silicon Laboratories Inc, C8051F300DK Datasheet - Page 103

• Manufacturer Part Number: C8051F300DK
• Description: DEV KIT F300/301/302/303/304/305
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F300DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F30x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F300
• Silicon Family Name: C8051F30x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F300/001/002
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1246

12. Port Input/Output
Digital and analog resources are available through a byte-wide digital I/O Port, Port0. Each of the Port pins
can be defined as general-purpose I/O (GPIO), analog input, or assigned to one of the internal digital
resources as shown in Figure 12.3. The designer has complete control over which functions are assigned,
limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the
use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corre-
sponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 12.3 and Figure 12.4). The registers XBR0, XBR1, and XBR2, defined in SFR Definition 12.1, SFR
Definition 12.2, and SFR Definition 12.3 are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 12.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port0 Output Mode register (P0MDOUT). Complete Electrical
Specifications for Port I/O are given in Table 12.1 on page 110.
Highest
Priority
Lowest
Priority
/WEAK-PULLUP
PUSH-PULL
/PORT-OUTENABLE
PORT-OUTPUT
ANALOG INPUT
PORT-INPUT
Figure 12.1. Port I/O Functional Block Diagram
SYSCLK
Outputs
SMBus
T0, T1
UART
PCA
CP0
Figure 12.2. Port I/O Cell Block Diagram
Port Latch
2
2
2
4
2
P0
Analog Select
(P0.0-P0.7)
8
Rev. 2.9
XBR2 Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
C8051F300/1/2/3/4/5
8
P0MDIN Registers
GND
VDD
P0MDOUT,
Cells
P0
I/O
VDD
(WEAK)
P0.0
P0.7
PORT
PAD
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