C8051F300DK Silicon Laboratories Inc, C8051F300DK Datasheet - Page 158

DEV KIT F300/301/302/303/304/305

C8051F300DK

Manufacturer Part Number
C8051F300DK
Description
DEV KIT F300/301/302/303/304/305
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F300DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F30x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F300
Silicon Family Name
C8051F30x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F300/001/002
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1246
C8051F300/1/2/3/4/5
16.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/
timer and copy it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
158
Port I/O
hardware.
Crossbar
Figure 16.4. PCA Capture Mode Diagram
CEXn
W
P
M
1
6
n
x
PCA0CPMn
O
M
E
C
n
0
Rev. 2.9
C
A
P
P
n
C
A
P
N
n
0
1
M
A
T
n
0 0 0 x
T
O
G
n
W
M
P
n
E
C
C
F
n
0
1
C
F
C
R
PCA0CN
PCA
Timebase
C
C
F
2
C
C
F
1
C
C
F
0
PCA Interrupt
Capture
PCA0CPLn
PCA0L
PCA0CPHn
PCA0H

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