C8051F300DK Silicon Laboratories Inc, C8051F300DK Datasheet - Page 105

• Manufacturer Part Number: C8051F300DK
• Description: DEV KIT F300/301/302/303/304/305
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F300DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F30x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F300
• Silicon Family Name: C8051F30x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F300/001/002
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1246

Registers XBR1 and XBR2 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL). Either or both of the UART signals may be selected by the Crossbar. UART0 pin assignments are
fixed for bootloading purposes: when UART TX0 is selected, it is always assigned to P0.4; when UART
RX0 is selected, it is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned. For example, if assigned functions that take the first 3 Port I/O (P0.[2:0]), 5
Port I/O are left for analog or GPIO use.
SF Signals
PIN I/O
TX0
RX0
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
SF Signals
Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44
VREF
0
0
Port pin potentially available to peripheral
Port pin skipped by CrossBar
Special Function Signals are not assigned by the crossbar. When
these signals are enabled, the CrossBar must be manually
configured to skip their corresponding port pins. Note: x1 refers to
the XTAL1 signal; x2 refers to the XTAL2 signal.
1
0
x1
2
1
XBR0[0:7]
x2
3
0
P0
4
0
Rev. 2.9
5
0
CNVSTR
6
1
7
0
C8051F300/1/2/3/4/5
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