C8051F300DK Silicon Laboratories Inc, C8051F300DK Datasheet - Page 86

• Manufacturer Part Number: C8051F300DK
• Description: DEV KIT F300/301/302/303/304/305
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F300DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F30x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F300
• Silicon Family Name: C8051F30x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F300/001/002
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1246

C8051F300/1/2/3/4/5
9.7.
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
•
•
•
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
9.8.
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
Table 9.2. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
86
Missing Clock Detector Timeout Time from last system clock ris-
V
RST Input Leakage Current
DD
Minimum RST Low Time to
Generate a System Reset
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a
MOVX operation is attempted above the user code space address limit.
A Flash read is attempted above user code space. This occurs when a MOVC operation is attempted
above the user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
Monitor Threshold (V
Reset Time Delay
Flash Error Reset
Software Reset
V
DD
Parameter
Ramp Time
C8051F300/1/2/3
Table 9.1. User Code Space Address Limits
C8051F304
C8051F305
RST
Device
)
reset source and code execution
Delay between release of any
I
OL
ing edge to reset initiation
= 8.5 mA, V
at location 0x0000
V
DD
RST = 0.0 V
Conditions
User Code Space Address Limit
= 0 to V
3.6 V
Rev. 2.9
DD
= 2.7 V to
RST
0x1DFF
0x0FFF
0x07FF
0.7 x V
2.40
Min
100
5.0
15
—
—
—
—
DD
2.55
Typ
220
25
—
—
—
—
—
—
0.3 x V
Max
2.70
500
0.6
40
—
—
—
1
DD
Units
ms
µA
µs
µs
µs
V
V
V