C8051F300DK Silicon Laboratories Inc, C8051F300DK Datasheet - Page 84

• Manufacturer Part Number: C8051F300DK
• Description: DEV KIT F300/301/302/303/304/305
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F300DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F30x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F300
• Silicon Family Name: C8051F30x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F300/001/002
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1246

C8051F300/1/2/3/4/5
9.1.
During powerup, the device is held in a reset state and the RST pin is driven low until V
V
ramp time increases (V
times (less than 1 ms), the power-on reset delay (T
Note: The maximum V
released from reset before V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a powerup was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
9.2.
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 9.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The V
monitor is disabled after power-on resets; however its defined state (enabled/disabled) is not altered by
any other reset source. For example, if the V
V
84
RST
DD
monitor will still be enabled after the reset. The V
. An additional delay occurs before the device is released from reset; the delay decreases as the V
Power-On Reset
Power-Fail Reset/V
Logic HIGH
Logic LOW
RST
Figure 9.2. Power-On and V
2.70
2.55
2.0
1.0
, the CIP-51 will be released from the reset state. Note that even though internal data
DD
DD
ramp time is defined as how fast V
/RST
ramp time is 1 ms; slower ramp times may cause the device to be
DD
DD
V
reaches the VRST level.
RST
Monitor
Power-On
Reset
DD
T
PORDelay
monitor is enabled and a software reset is performed, the
Rev. 2.9
PORDelay
DD
DD
monitor is enabled by writing a ‘1’ to the PORSF
Monitor Reset Timing
) is typically less than 0.3 ms.
DD
DD
ramps from 0 V to V
to drop below V
Monitor
Reset
VDD
DD
monitor is disabled following a
RST
VDD
RST
, the power supply
DD
DD
). For valid ramp
t
dropped below
settles above
DD
returns
DD
DD