C8051F300DK Silicon Laboratories Inc, C8051F300DK Datasheet - Page 152

• Manufacturer Part Number: C8051F300DK
• Description: DEV KIT F300/301/302/303/304/305
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F300DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F30x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F300
• Silicon Family Name: C8051F30x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F300/001/002
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1246

C8051F300/1/2/3/4/5
15.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 15.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
Note: External clock divided by 8 is synchronized with the system clock, and the external clock must be
less than or equal to the system clock to operate in this mode.
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
152
T2MH
External Clock / 8
0
0
1
SYSCLK / 12
T2XCLK TMR2H Clock Source
X
0
1
T2XCLK
0
1
Figure 15.5. Timer 2 8-Bit Mode Block Diagram
External Clock / 8
SYSCLK
SYSCLK / 12
SYSCLK
0
1
1
0
M
H
T
2
CKCON
M
T
2
L
M
T
1
M
T
0
TR2
C
S
A
1
S
C
A
0
Rev. 2.9
TCLK
TCLK
TMR2RLH
TMR2RLL
TMR2H
TMR2L
T2ML
0
0
1
Reload
Reload
T2XCLK TMR2L Clock Source
X
0
1
To SMBus
To ADC,
T2SPLIT
TF2LEN
T2XCLK
SMBus
TF2H
TF2L
TR2
External Clock / 8
SYSCLK / 12
SYSCLK
Interrupt