C8051F996DK Silicon Laboratories Inc, C8051F996DK Datasheet - Page 146
![KIT DEV FOR C8051F996](/photos/28/41/284142/c8051f996dk_sml.jpg)
C8051F996DK
Manufacturer Part Number
C8051F996DK
Description
KIT DEV FOR C8051F996
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051F996DK.pdf
(24 pages)
2.C8051F996DK.pdf
(2 pages)
3.C8051F996DK.pdf
(4 pages)
4.C8051F996DK.pdf
(322 pages)
Specifications of C8051F996DK
Contents
Board, Batteries, Cables, CDs, Debug Adapter, Documentation, Power Adapter
Processor To Be Evaluated
C8051F996
Processor Series
C8051F98x
Interface Type
USB
Operating Supply Voltage
3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F996
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1963
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C8051F99x-C8051F98x
SFR Definition 13.6. EIP2: Extended Interrupt Priority 2
SFR Page = All; SFR Address = 0xF7
146
Name
Reset
Type
Bit
Bit
7
6
5
4
3
2
1
0
PCSEOS Capacitive Sense End of Scan Interrupt Priority Control.
PCSCPT Capacitive Sense Conversion Complete Interrupt Priority Control.
PRTC0F SmaRTClock Oscillator Fail Interrupt Priority Control.
PWARN Supply Monitor Early Warning Interrupt Priority Control.
PCSDC Capacitive Sense Digital Comparator Interrupt Priority Control.
Unused Read = 0b. Write = Don’t care.
Unused Read = 0b. Write = Don’t care.
Name
PMAT
R
7
0
0: Capacitive Sense End of Scan interrupt set to low priority level.
1: Capacitive Sense End of Scan interrupt set to high priority level.
0: Capacitive Sense Digital Comparator interrupt set to low priority level.
1: Capacitive Sense Digital Comparator interrupt set to high priority level.
0: Capacitive Sense Conversion Complete interrupt set to low priority level.
1: Capacitive Sense Conversion Complete interrupt set to high priority level.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
This bit sets the priority of the Supply Monitor Early Warning interrupt.
0: Supply Monitor Early Warning interrupt set to low priority level.
1: Supply Monitor Early Warning interrupt set to high priority level.
PCSEOS
R/W
6
0
PCSDC
R/W
5
0
PCSCPT
R/W
Rev. 1.0
4
0
Function
R
3
0
PRTC0F
R/W
2
0
PMAT
R/W
1
0
PWARN
R/W
0
0
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