C8051F996DK Silicon Laboratories Inc, C8051F996DK Datasheet - Page 179
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C8051F996DK
Manufacturer Part Number
C8051F996DK
Description
KIT DEV FOR C8051F996
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051F996DK.pdf
(24 pages)
2.C8051F996DK.pdf
(2 pages)
3.C8051F996DK.pdf
(4 pages)
4.C8051F996DK.pdf
(322 pages)
Specifications of C8051F996DK
Contents
Board, Batteries, Cables, CDs, Debug Adapter, Documentation, Power Adapter
Processor To Be Evaluated
C8051F996
Processor Series
C8051F98x
Interface Type
USB
Operating Supply Voltage
3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F996
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1963
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18. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
All SFRs are reset to the predefined values noted in the SFR descriptions. The contents of RAM are
unaffected during a reset; any previously stored data is preserved as long as power is not lost. Since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal
oscillator. Refer to Section “19. Clocking Sources” on page 186 for information on selecting and
configuring the system clock source. The Watchdog Timer is enabled with the system clock divided by 12
as its clock source (Section “26.4. Watchdog Timer Mode” on page 309 details the use of the Watchdog
Timer). Program execution begins at location 0x0000.
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled
Px.x
Px.x
SmaRTClock
System
Clock
Comparator 0
RTC0RE
+
-
C0RSEF
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
DD
CIP-51
Handler
Core
Monitor and power-on resets, the RST pin is driven low until the device
Figure 18.1. Reset Sources
WDT
PCA
EN
VDD
System Reset
Supply
Monitor
+
-
Rev. 1.0
Enable
C8051F99x-C8051F98x
(Software Reset)
SWRSF
(wired-OR)
Power Management
Block (PMU0)
'0'
Power On
Reset
VDD
Illegal Flash
Reset
Operation
System Reset
Power-On Reset
Funnel
Reset
RST
179
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